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DM6437 McBSP Driver question; purpose of PAL_osWaitMsecs(2) delay statements?

Brad L
Intellectual 1245 points


We have found a couple of PAL_osWaitMsecs(2); statements in the ddc_mcbsp.c file under the DDC_McBspSpiTransfer() function.  Can you tell us or find out from the drivers group for us why these calls were put there and if they’re necessary? It’s forcing us to put in delays on the SPI master side and SPI is our primary communications channel.  Here are the comments in the file.


            /*

            5.  After the sample rate generator is released from reset,

                wait two sample rate generator clock periods for

                the McBSP logic to stabilize.*/

            PAL_osWaitMsecs(2);

 

          /*

          7.    After the transmitter and receiver are released from reset, wait

                two sample rate generator clock periods for the McBSP logic

                to stabilize.*/

          PAL_osWaitMsecs(2);

Can someone provide more insight it would be helpful.

Brad

  • 0
    TI__Genius 9490 points

    Brad,

    The actual requirement delay from the MCBSP perspective (as listed in the Mcbsp users guide(http://focus.ti.com/lit/ug/spru943c/spru943c.pdf) section 2.11.1) for internal logic synchronization is the reason for the sw to add this delay.  I'm not sure if those specific function calls are in 'Milli' or 'Micro' seconds or what, but depending if the clk is driven by an external or internal master the wait required should be for 2 external CLKR/X cycles, or 2 internal CLKSRG cycles.  So whatever the CLKX/R(external) or CLKSRG(internal) cycles frequencies are then the corresponding time in seconds should be calculated.  This applies to both places in the initialization process again to internal logic synchronization to take place.

    "Wait for proper internal synchronization. If the external device provides the bit clock, wait for two CLKR or CLKX cycles. If the McBSP generates the bit clock as a clock master, wait for two CLKSRG cycles. In this case, the clock source to the sample rate generator (CLKSRG) is selected by the CLKSM bit in SRGR and the SCLKME bit in PCR."

     

    regards,

    miguel

     

  • 0 in reply to Miguel A. Alanis
    Expert 1005 points

    Are we talking about the SPI clock?  Why would this be hard coded to 2 milliseconds?