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[C6678] Active clocks before chip powered

TimHarron
Mastermind 18130 points


The power supply for the DSP clocks will be on before the DSP voltages are up , so the clocks will be toggling on the DSP before it is powered. From the reset timing diagram this may be ok, but I wanted to make sure that toggling clock inputs before the DSP is powered will not be a problem. From the reset timing diagram:

- Once CVDD is valid, the clock drivers should be enabled. Although the clock inputs are not necessary at this time, they should either be driven with a valid clock or be held in a static state with one leg high and one leg low.

- The DDRCLK and REFCLK may begin to toggle anytime between when CVDD is at a valid level and the setup time before POR goes high specified by t7.

 

  • 0
    TI__Mastermind 42545 points

    CVDD must be valid before any of the clock inputs begin to toggle or are driven high.  Before CVDD is valid the clock inputs must either be held at ground or left floating.  CVDD is the power supply for the clock input buffers and applying an voltage to these pins before the CVDD power supply is present may damage the IO buffer.  If the clock input is unused the negative leg should be tied to ground through a resistor and the positive leg tied to CVDD.  This will ensure that an input voltage is not applied before the clock buffer is powered.