TDA4VM: the problem in TVM with last inference scirpts.

root@j7-evm:~/debu/yolov5_onnx# python3 yolo_onnx_inference_tidl.py --infer
libtidl_onnxrt_EP loaded 0x17898e00
Final number of subgraphs created are : 1, - Offloaded Nodes - 320, Total Nodes - 320
APP: Init ... !!!
MEM: Init ... !!!
MEM: Initialized DMA HEAP (fd=4) !!!
MEM: Init ... Done !!!
IPC: Init ... !!!
IPC: Init ... Done !!!
REMOTE_SERVICE: Init ... !!!
REMOTE_SERVICE: Init ... Done !!!
 11435.424450 s: GTC Frequency = 200 MHz
APP: Init ... Done !!!
 11435.424517 s:  VX_ZONE_INIT:Enabled
 11435.424526 s:  VX_ZONE_ERROR:Enabled
 11435.424540 s:  VX_ZONE_WARNING:Enabled
 11435.425100 s:  VX_ZONE_INIT:[tivxInitLocal:130] Initialization Done !!!
 11435.426230 s:  VX_ZONE_INIT:[tivxHostInitLocal:86] Initialization Done for HOST !!!
Starting Inference
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 11436.395001 s:  VX_ZONE_INIT:[tivxHostDeInitLocal:100] De-Initialization Done for HOST !!!
 11436.399369 s:  VX_ZONE_INIT:[tivxDeInitLocal:193] De-Initialization Done !!!
APP: Deinit ... !!!
REMOTE_SERVICE: Deinit ... !!!
REMOTE_SERVICE: Deinit ... Done !!!
IPC: Deinit ... !!!
IPC: DeInit ... Done !!!
MEM: Deinit ... !!!
MEM: Alloc's: 7 alloc's of 15935413 bytes
MEM: Free's : 7 free's  of 15935413 bytes
MEM: Open's : 0 allocs  of 0 bytes
MEM: Deinit ... Done !!!
APP: Deinit ... Done !!!

# dependencies
# Anaconda Python 3.7 for Linux - download and install from: https://www.anaconda.com/distribution/
# pytorch, torchvision - install using: conda install pytorch torchvision -c pytorch
# timm - install using: pip install timm

import os
import numpy as np
import cv2
import argparse
import onnxruntime as rt


parser = argparse.ArgumentParser()
parser.add_argument("--model_path", type=str, default="./yolov5s6_640_ti_lite_37p4_56p0.onnx")
parser.add_argument("--model_prototxt", type=str, default="./yolov5s6_640_ti_lite_metaarch.prototxt")
parser.add_argument("--img_calib_path", type=str, default="./sample_calib_ips_640x640.txt")
parser.add_argument("--img_path", type=str, default="./sample_ips_640x640.txt")
parser.add_argument("--dst_path", type=str, default="./sample_ops_onnxrt_det")
parser.add_argument("--compile", default=False, action="store_true")
parser.add_argument("--inference", default=False, action="store_true")

args = parser.parse_args()
output_dir =  "./artifacts/"
os.makedirs(output_dir, exist_ok=True)

if args.compile:
    for root, dirs, files in os.walk(output_dir, topdown=False):
        [os.remove(os.path.join(root, f)) for f in files]
        [os.rmdir(os.path.join(root, d)) for d in dirs]

calibration_frames = 2
calibration_iterations = 5

compile_options = {
"artifacts_folder": "./artifacts/",
"tensor_bits":8,
"accuracy_level":1,
#"debug_level": 3,
"advanced_options:calibration_frames": calibration_frames,
"advanced_options:calibration_iterations": calibration_iterations,
"advanced_options:output_feature_16bit_names_list" : "370, 680, 990, 1300",
'object_detection:meta_layers_names_list' : args.model_prototxt,
'object_detection:meta_arch_type' : 6,
"ti_internal_nc_flag" : 1601,
#"add_data_convert_ops" : 3,
}

if args.inference:
    compile_options["tidl_tools_path"] = ""
else:
    compile_options["tidl_tools_path"] = os.environ["TIDL_TOOLS_PATH"]

so = rt.SessionOptions()
# EP_list = ['TIDLCompilationProvider','CPUExecutionProvider']
# sess = rt.InferenceSession(args.model_path ,providers=EP_list, provider_options=[compile_options, {}], sess_options=so)
# input_details = sess.get_inputs()


_CLASS_COLOR_MAP = [
    (0, 0, 255) , # Person (blue).
    (255, 0, 0) ,  # Bear (red).
    (0, 255, 0) ,  # Tree (lime).
    (255, 0, 255) ,  # Bird (fuchsia).
    (0, 255, 255) ,  # Sky (aqua).
    (255, 255, 0) ,  # Cat (yellow).
]


def read_img(img_file, img_mean=127.5, img_scale=1/127.5):
    img = cv2.imread(img_file)[:, :, ::-1]
    img = cv2.resize(img, (640,640), interpolation=cv2.INTER_LINEAR)
    img = (img - img_mean) * img_scale
    img = np.asarray(img, dtype=np.float32)
    img = np.expand_dims(img,0)
    img = img.transpose(0,3,1,2)
    return img


def model_import_image_list_tidl(model_path, img_path=None, mean=None, scale=None):
    "model compilation"
    img_file_list = list(open(img_path))[:calibration_frames]
    EP_list = ['TIDLCompilationProvider','CPUExecutionProvider']
    sess = rt.InferenceSession(model_path ,providers=EP_list, provider_options=[compile_options, {}], sess_options=so)

    input_name = sess.get_inputs()[0].name
    for img_index, img_file  in enumerate(img_file_list):
        img_file = img_file.split(' ')[0].rstrip()
        input = read_img(img_file, mean, scale)
        output = sess.run([], {input_name: input})


def model_infer_image_list_tidl(model_path, img_path=None, mean=None, scale=None, dst_path=None):
    "inference on sample images"
    os.makedirs(args.dst_path, exist_ok=True)
    EP_list = ['TIDLExecutionProvider','CPUExecutionProvider']
    sess = rt.InferenceSession(model_path ,providers=EP_list, provider_options=[compile_options, {}], sess_options=so)
    input_name = sess.get_inputs()[0].name
    img_file_list = list(open(img_path))
    max_index = 20
    print("Starting Inference")
    for img_index, img_file  in enumerate(img_file_list):
        print(f"{img_index+1}/{len(img_file_list)}")
        img_file = img_file.split(' ')[0].rstrip()
        input = read_img(img_file, mean, scale)
        output = sess.run([], {input_name: input})
        output = np.squeeze(output[0])
        dst_file = os.path.join(dst_path, os.path.basename(img_file))
        post_process(img_file, dst_file, output, score_threshold=0.5)



def post_process(img_file, dst_file, output, score_threshold=0.3):
    """
    Draw bounding boxes on the input image. Dump boxes in a txt file.
    """
    det_bboxes, det_scores, det_labels = output[:, 0:4], output[:, 4], output[:, 5]
    img = cv2.imread(img_file)
    #To generate color based on det_label, to look into the codebase of Tensorflow object detection api.
    dst_txt_file = dst_file.replace('png', 'txt')
    f = open(dst_txt_file, 'wt')
    for idx in range(len(det_bboxes)):
        det_bbox = det_bboxes[idx]
        if det_scores[idx]>0:
            f.write("{:8.0f} {:8.5f} {:8.5f} {:8.5f} {:8.5f} {:8.5f}\n".format(det_labels[idx], det_scores[idx], det_bbox[1], det_bbox[0], det_bbox[3], det_bbox[2]))
        if det_scores[idx]>score_threshold:
            color_map = _CLASS_COLOR_MAP[int(det_labels[idx]) %len(_CLASS_COLOR_MAP)]
            img = cv2.rectangle(img, (int(det_bbox[0]), int(det_bbox[1])), (int(det_bbox[2]), int(det_bbox[3])), color_map[::-1], 2)
            cv2.putText(img, "id:{}".format(int(det_labels[idx])), (int(det_bbox[0]+5),int(det_bbox[1])+15), cv2.FONT_HERSHEY_SIMPLEX, 0.5, color_map[::-1], 2)
            cv2.putText(img, "score:{:2.1f}".format(det_scores[idx]), (int(det_bbox[0] + 5), int(det_bbox[1]) + 30), cv2.FONT_HERSHEY_SIMPLEX, 0.5, color_map[::-1], 2)
    cv2.imwrite(dst_file, img)
    f.close()



def main():
    if args.compile:
        model_import_image_list_tidl(model_path=args.model_path, img_path=args.img_calib_path,
                                   mean=0.0, scale=0.00392156862745098)
    elif args.inference:
        model_infer_image_list_tidl(model_path=args.model_path, img_path=args.img_path,
                               mean=0.0, scale=0.00392156862745098,
                               dst_path=args.dst_path)


if __name__== "__main__":
    main()

[BEGIN] 2022-09-02 ���� 11:18:58
root@j7-evm:/opt/edgeai-tidl-tools/yolov5_onnx_0728# export TIDL_RT_DEBUG=3^C
del_prototxt ./yolov5s6_640ti_lite_metaarch.prototxt --inference
Traceback (most recent call last):
  File "yolo_onnx_inference_tidl.py", line 52, in <module>
    compile_options["tidl_tools_path"] = os.environ["TIDL_TOOLS_PATH"]
  File "/usr/lib/python3.8/os.py", line 675, in __getitem__
    raise KeyError(key) from None
KeyError: 'TIDL_TOOLS_PATH'
root@j7-evm:/opt/edgeai-tidl-tools/yolov5_onnx_0728# echo $TIDL_TOOLS_PATH
/usr/lib
root@j7-evm:/opt/edgeai-tidl-tools/yolov5_onnx_0728# python3 yolo_onnx_inference_tidl.py --model_path ./yolov5s6_640_ti_lite_37p4_56p0.onnx --model_prototxt ./yolov5s6_640ti_lite_metaarch.prototxt --inference
libtidl_onnxrt_EP loaded 0x29504510 
artifacts_folder                                = ./artifacts/ 
debug_level                                     = 1 
Parsing ONNX Model 
Final number of subgraphs created are : 1, - Offloaded Nodes - 320, Total Nodes - 320 
In TIDL_createStateCommon 
Compute on node : TIDLExecutionProvider_TIDL_0_0
  0,            Conv, 3, 1, images, 167
  1,            Relu, 1, 1, 167, 168
  2,            Conv, 3, 1, 168, 169
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 84,         MaxPool, 1, 1, 250, 254
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 88,            Conv, 3, 1, 257, 258
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102,            Relu, 1, 1, 271, 272
103,          Resize, 3, 1, 272, 277
104,          Concat, 2, 1, 277, 278
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118,          Resize, 3, 1, 291, 296
119,          Concat, 2, 1, 296, 297
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133,          Resize, 3, 1, 310, 315
134,          Concat, 2, 1, 315, 316
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143,          Concat, 2, 1, 322, 325
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146,            Conv, 3, 1, 327, 370
147,         Reshape, 2, 1, 370, 388
148,       Transpose, 1, 1, 388, 389
149,         Sigmoid, 1, 1, 389, 390
150,           Slice, 5, 1, 390, 395
151,             Mul, 2, 1, 395, 397
152,             Sub, 2, 1, 397, 399
153,             Add, 2, 1, 399, 401
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155,         Reshape, 2, 1, 403, 410
156,          Expand, 2, 1, 410, 420
157,         Reshape, 2, 1, 420, 530
158,       ScatterND, 3, 1, 390, 531
159,           Slice, 5, 1, 531, 536
160,             Mul, 2, 1, 536, 538
161,             Pow, 2, 1, 538, 541
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165,         Reshape, 2, 1, 561, 671
166,       ScatterND, 3, 1, 531, 672
167,         Reshape, 2, 1, 672, 679
168,            Conv, 3, 1, 327, 328
169,            Relu, 1, 1, 328, 329
170,          Concat, 2, 1, 329, 330
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182,            Conv, 3, 1, 341, 680
183,         Reshape, 2, 1, 680, 698
184,       Transpose, 1, 1, 698, 699
185,         Sigmoid, 1, 1, 699, 700
186,           Slice, 5, 1, 700, 705
187,             Mul, 2, 1, 705, 707
188,             Sub, 2, 1, 707, 709
189,             Add, 2, 1, 709, 711
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191,         Reshape, 2, 1, 713, 720
192,          Expand, 2, 1, 720, 730
193,         Reshape, 2, 1, 730, 840
194,       ScatterND, 3, 1, 700, 841
195,           Slice, 5, 1, 841, 846
196,             Mul, 2, 1, 846, 848
197,             Pow, 2, 1, 848, 851
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199,         Reshape, 2, 1, 854, 861
200,          Expand, 2, 1, 861, 871
201,         Reshape, 2, 1, 871, 981
202,       ScatterND, 3, 1, 841, 982
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204,            Conv, 3, 1, 341, 342
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229,         Reshape, 2, 1, 1040, 1150
230,       ScatterND, 3, 1, 1010, 1151
231,           Slice, 5, 1, 1151, 1156
232,             Mul, 2, 1, 1156, 1158
233,             Pow, 2, 1, 1158, 1161
234,             Mul, 2, 1, 1161, 1164
235,         Reshape, 2, 1, 1164, 1171
236,          Expand, 2, 1, 1171, 1181
237,         Reshape, 2, 1, 1181, 1291
238,       ScatterND, 3, 1, 1151, 1292
239,         Reshape, 2, 1, 1292, 1299
240,            Conv, 3, 1, 355, 356
241,            Relu, 1, 1, 356, 357
242,          Concat, 2, 1, 357, 358
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260,             Sub, 2, 1, 1327, 1329
261,             Add, 2, 1, 1329, 1331
262,             Mul, 2, 1, 1331, 1333
263,         Reshape, 2, 1, 1333, 1340
264,          Expand, 2, 1, 1340, 1350
265,         Reshape, 2, 1, 1350, 1460
266,       ScatterND, 3, 1, 1320, 1461
267,           Slice, 5, 1, 1461, 1466
268,             Mul, 2, 1, 1466, 1468
269,             Pow, 2, 1, 1468, 1471
270,             Mul, 2, 1, 1471, 1474
271,         Reshape, 2, 1, 1474, 1481
272,          Expand, 2, 1, 1481, 1491
273,         Reshape, 2, 1, 1491, 1601
274,       ScatterND, 3, 1, 1461, 1602
275,         Reshape, 2, 1, 1602, 1609
276,          Concat, 4, 1, 679, 1610
277,           Split, 1, 1, 1610, 1616
278,         Squeeze, 1, 1, 1616, 1617
279,          Gather, 2, 1, 1610, 1612
280,            Cast, 1, 1, 1612, 1613
281,         Greater, 2, 1, 1613, 1615
282,          Gather, 2, 1, 1615, 1619
283,         NonZero, 1, 1, 1619, 1621
284,       Transpose, 1, 1, 1621, 1622
285,         Squeeze, 1, 1, 1622, 1623
286,          Gather, 2, 1, 1617, 1624
287,           Slice, 5, 1, 1624, 1629
288,           Slice, 5, 1, 1624, 1639
289,             Div, 2, 1, 1639, 1658
290,             Sub, 2, 1, 1629, 1662
291,           Slice, 5, 1, 1624, 1634
292,           Slice, 5, 1, 1624, 1644
293,             Div, 2, 1, 1644, 1661
294,             Sub, 2, 1, 1634, 1663
295,             Add, 2, 1, 1629, 1664
296,             Add, 2, 1, 1634, 1665
297,           Slice, 5, 1, 1624, 1649
298,           Slice, 5, 1, 1624, 1654
299,             Mul, 2, 1, 1649, 1655
300,          ArgMax, 1, 1, 1655, 1668
301,            Cast, 1, 1, 1668, 1669
302,       ReduceMax, 1, 1, 1655, 1667
303,          Concat, 6, 1, 1662, 1670
304,         Reshape, 2, 1, 1667, 1672
305,            Cast, 1, 1, 1672, 1673
306,         Greater, 2, 1, 1673, 1675
307,         NonZero, 1, 1, 1675, 1677
308,       Transpose, 1, 1, 1677, 1678
309,         Squeeze, 1, 1, 1678, 1679
310,          Gather, 2, 1, 1670, 1680
311,           Slice, 5, 1, 1680, 1685
312,       Unsqueeze, 1, 1, 1685, 1688
313,          Gather, 2, 1, 1680, 1687
314,       Unsqueeze, 1, 1, 1687, 1689
315,       Unsqueeze, 1, 1, 1689, 1690
316, NonMaxSuppression, 4, 1, 1688, 1693
317,          Gather, 2, 1, 1693, 1695
318,         Squeeze, 1, 1, 1695, 1696
319,          Gather, 2, 1, 1680, detections

Input tensor name -  images 
Output tensor name - detections 
************ in TIDL_subgraphRtCreate ************ 
 TIDL_RT_OVX: Set default TIDLRT params done
Calling appInit() in TIDL-RT!
APP: Init ... !!!
MEM: Init ... !!!
MEM: Initialized DMA HEAP (fd=4) !!!
MEM: Init ... Done !!!
IPC: Init ... !!!
IPC: Init ... Done !!!
REMOTE_SERVICE: Init ... !!!
REMOTE_SERVICE: Init ... Done !!!
   942.991766 s: GTC Frequency = 200 MHz
APP: Init ... Done !!!
   942.995056 s:  VX_ZONE_INIT:Enabled
   942.995079 s:  VX_ZONE_ERROR:Enabled
   942.995085 s:  VX_ZONE_WARNING:Enabled
   942.999187 s:  VX_ZONE_INIT:[tivxInitLocal:130] Initialization Done !!!
   942.999391 s:  VX_ZONE_INIT:[tivxHostInitLocal:86] Initialization Done for HOST !!!
TIDL_RT_OVX: Init ... 
TIDL_RT_OVX: Mapping config file ...
TIDL_RT_OVX: Mapping config file ... Done. 37256 bytes
TIDL_RT_OVX: Tensors, input = 1, output = 1
TIDL_RT_OVX: Mapping network file
TIDL_RT_OVX: Mapping network file... Done 14632192 bytes
TIDL_RT_OVX: Init done.
TIDL_RT_OVX: Creating graph ... 
TIDL_RT_OVX: input_sizes[0] = 641, dim = 640 padL = 1 padR = 0
TIDL_RT_OVX: input_sizes[1] = 412163, dim = 640 padT = 1 padB = 2
TIDL_RT_OVX: input_sizes[2] = 3, dim = 3 
TIDL_RT_OVX: input_sizes[3] = 1, dim = 1 
TIDL_RT_OVX: input_buffer = 0xffff79c20000 1236489
TIDL_RT_OVX: Creating graph ... Done.
[C7x_1 ]    943.035011 s:  VX_ZONE_INFO:[tivxAlgiVisionAllocMem:172] Allocating memory record 0 @ space = 17, size = 15208, align = 128 ... 
[C7x_1 ]    943.034979 s:  VX_ZONE_INFO:Enabled
.. 
[C7x_1 ]    943.035075 s:  VX_ZONE_INFO:[tivxAlgiVisionAllocMem:172] Allocating memory record 1 @ space = 17, size = 136, align = 128 ... 
[C7x_1 ]    943.035075 s:  VX_ZONE_INFO:[tivxAlgiVisionAllocMem:172] Allocating memory record 1 @ space = 17, size = 136, align = 128 ... 
 
 
[C7x_1 ]    943.035132 s:  VX_ZONE_INFO:[tivxAlgiVisionAllocMem:172] Allocating memory record 2 @ space = 0, size = 16384, align = 128 ... 
[C7x_1 ]    943.035132 s:  VX_ZONE_INFO:[tivxAlgiVisionAllocMem:172] Allocating memory record 2 @ space = 0, size = 16384, align = 128 ... 
 
 
[C7x_1 ]    943.035189 s:  VX_ZONE_INFO:[tivxAlgiVisionAllocMem:172] Allocating memory record 3 @ space = 1, size = 458752, align = 128 ... 
[C7x_1 ]    943.035189 s:  VX_ZONE_INFO:[tivxAlgiVisionAllocMem:172] Allocating memory record 3 @ space = 1, size = 458752, align = 128 ... 
. 
. 
[C7x_1 ]    943.035246 s:  VX_ZONE_INFO:[tivxAlgiVisionAllocMem:172] Allocating memory record 4 @ space = 2, size = 8159232, align = 128 ... 
[C7x_1 ]    943.035246 s:  VX_ZONE_INFO:[tivxAlgiVisionAllocMem:172] Allocating memory record 4 @ space = 2, size = 8159232, align = 128 ... 
.. 
.. 
[C7x_1 ]    943.035304 s:  VX_ZONE_INFO:[tivxAlgiVisionAllocMem:172] Allocating memory record 5 @ space = 17, size = 14207920, align = 128 ... 
[C7x_1 ]    943.035304 s:  VX_ZONE_INFO:[tivxAlgiVisionAllocMem:172] Allocating memory record 5 @ space = 17, size = 14207920, align = 128 ... 
0 ... 
0 ... 
[C7x_1 ]    943.035481 s:  VX_ZONE_INFO:[tivxAlgiVisionAllocMem:172] Allocating memory record 6 @ space = 17, size = 256, align = 128 ... 
[C7x_1 ]    943.035481 s:  VX_ZONE_INFO:[tivxAlgiVisionAllocMem:172] Allocating memory record 6 @ space = 17, size = 256, align = 128 ... 
[C7x_1 ]    943.035509 s:  VX_ZONE_INFO:[tivxAlgiVisionAllocMem:181] Allocated memory record 6 @ space = 17 and size = 256, addr = e4000000 ... 
[C7x_1 ]    943.035509 s:  VX_ZONE_INFO:[tivxAlgiVisionAllocMem:181] Allocated memory record 6 @ space = 17 and size = 256, addr = e4000000 ... 
[C7x_1 ]    943.035537 s:  VX_ZONE_INFO:[tivxAlgiVisionAllocMem:172] Allocating memory record 7 @ space = 17, size = 2471676, align = 128 ... 
[C7x_1 ]    943.035537 s:  VX_ZONE_INFO:[tivxAlgiVisionAllocMem:172] Allocating memory record 7 @ space = 17, size = 2471676, align = 128 ... 
 ... 
 ... 
[C7x_1 ]    943.035608 s:  VX_ZONE_INFO:[tivxAlgiVisionAllocMem:172] Allocating memory record 8 @ space = 17, size = 128, align = 128 ... 
[C7x_1 ]    943.035608 s:  VX_ZONE_INFO:[tivxAlgiVisionAllocMem:172] Allocating memory record 8 @ space = 17, size = 128, align = 128 ... 
[C7x_1 ]    943.035637 s:  VX_ZONE_INFO:[tivxAlgiVisionAllocMem:181] Allocated memory record 8 @ space = 17 and size = 128, addr = e4000400 ... 
[C7x_1 ]    943.035637 s:  VX_ZONE_INFO:[tivxAlgiVisionAllocMem:181] Allocated memory record 8 @ space = 17 and size = 128, addr = e4000400 ... 
[C7x_1 ]    943.035665 s:  VX_ZONE_INFO:[tivxAlgiVisionAllocMem:172] Allocating memory record 9 @ space = 17, size = 3200, align = 128 ... 
[C7x_1 ]    943.035665 s:  VX_ZONE_INFO:[tivxAlgiVisionAllocMem:172] Allocating memory record 9 @ space = 17, size = 3200, align = 128 ... 
 
 
[C7x_1 ]    943.035721 s:  VX_ZONE_INFO:[tivxAlgiVisionAllocMem:172] Allocating memory record 10 @ space = 17, size = 5431680, align = 128 ... 
[C7x_1 ]    943.035721 s:  VX_ZONE_INFO:[tivxAlgiVisionAllocMem:172] Allocating memory record 10 @ space = 17, size = 5431680, align = 128 ... 
0 ... 
0 ... 
[C7x_1 ]    943.035813 s:  VX_ZONE_INFO:[tivxAlgiVisionAllocMem:172] Allocating memory record 11 @ space = 17, size = 1211776, align = 128 ... 
[C7x_1 ]    943.035813 s:  VX_ZONE_INFO:[tivxAlgiVisionAllocMem:172] Allocating memory record 11 @ space = 17, size = 1211776, align = 128 ... 
0 ... 
0 ... 
[C7x_1 ]    943.035872 s:  VX_ZONE_INFO:[tivxAlgiVisionAllocMem:172] Allocating memory record 12 @ space = 17, size = 1600783, align = 128 ... 
[C7x_1 ]    943.035872 s:  VX_ZONE_INFO:[tivxAlgiVisionAllocMem:172] Allocating memory record 12 @ space = 17, size = 1600783, align = 128 ... 
 ... 
 ... 
[C7x_1 ]    943.035930 s:  VX_ZONE_INFO:[tivxAlgiVisionAllocMem:172] Allocating memory record 13 @ space = 17, size = 8388608, align = 128 ... 
[C7x_1 ]    943.035930 s:  VX_ZONE_INFO:[tivxAlgiVisionAllocMem:172] Allocating memory record 13 @ space = 17, size = 8388608, align = 128 ... 
0 ... 
0 ... 
[C7x_1 ]    943.036046 s:  VX_ZONE_INFO:Disabled
TIDL_RT_OVX: Verifying TIDL graph ... Done.
************ TIDL_subgraphRtCreate done ************ 
Starting Inference
1/8
1/8 read_img
1/8 sess.run
 *******   In TIDL_subgraphRtInvoke  ******** 
TIDL_RT_OVX: Set default TIDLRT tensor done
TIDL_RT_OVX: Set default TIDLRT tensor done
TIDL_RT_OVX: Running Graph ... 
TIDL_RT_OVX : ElementType - 1, 6 
TIDL_RT_OVX: input_sizes[0] = 641, dim = 640 padL = 1 padR = 0
TIDL_RT_OVX: input_sizes[1] = 412163, dim = 640 padT = 1 padB = 2
TIDL_RT_OVX: input_sizes[2] = 3, dim = 3 
TIDL_RT_OVX: input_sizes[3] = 1, dim = 1 
TIDL_RT_OVX : ElementType - 1, 6 
TIDL_RT_OVX : Reformat input Buffer 
TIDL_RT_OVX : ElementType - 6, 1 | Scale - 1.000000, 128.000000 | Zp - 0, 0 | Layout - 0, 0 | CP - 412163, 409600
TIDL_RT_OVX: input_buffer = 0xffff79c20000 1236489
TIDL_RT_OVX: memset_out_tensor_tidlrt_tiovx  ... Done.
^C^Cexit
reboot