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connecting to nand flash

young li
Prodigy 10 points

According to UG(EMIF16) :The EMIF16 module is intended to provide a glue-less interface to a variety of asynchronous memory devices like ASRAM, NOR and NAND memory. A total of 256M bytes of any of these memories can be accessed at any given time via four chip selects with 64M byte access per chip select.

q:Does 6678 support a maximum addressing of 64M byte NAND FLASH over a chip select . if not , is there a limit of addressing when interfaceing a NAND FLASH with 6678 over one chip select?

  • 0
    TI__Expert 6815 points

    Young,

    The 64MB limit per chip-select is only for asynchronous memories that use the EMIF16's address bus for addressing ie NOR and SRAM.

    NAND uses the EMIF16's data bus for both addressing and data (multiplexed). The address bus is only used for CLE and ALE signals. The software is responsible for sending the address to NAND via the data bus over multiple addressing cycles (This should be present in your NAND device datasheet). Therefore, you should be able to address more than 64MB of NAND on a single chip-select. This clarification for NAND will be added to the next users guide release.

    * The only limitations that EMIF16 has for NAND are:

        1. It only supports 4-bit ECC over 512-byte page. It does not support a NAND that requires greater than 4-bit ECC.

        2. It does not support NAND Flashes that require the chip select to stay low during the tR time for a read - This will also be added to the next release.


    Please let me know if you have additional questions.

  • 0 in reply to Aditya
    TI__Expert 6815 points

    Young, the updated EMIF16 users guide with above clarifications is now available here.