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TDA4VM: 0C reference design of PMIC

Cherry Zhou
Mastermind 22235 points
Part Number: TDA4VM

Hi team,

Here's an issue from the customer may need your help:

In the 0C reference design of the PMIC, GPIO4 of PTPS65941213RWERQ1 is configured to WAKE signal. Is the state of this signal must be a change in the high or low level, or is it ok to be high all the time?
For example, GPIO4 is high when PTPS65941213RWERQ1 is working properly, and then GPIO4 is always high during PTPS65941213RWERQ1 going from active to LP_standby. Then the LP_standby state is also high, will the PMIC go back to active?

Could you help check this case? Thanks.

Best Regards,

Cherry

  • 0
    TI__Guru 64261 points

    Hello,

    Cherry Zhou said:
    In the 0C reference design of the PMIC, GPIO4 of PTPS65941213RWERQ1 is configured to WAKE signal. Is the state of this signal must be a change in the high or low level, or is it ok to be high all the time?

    The on request is edge sensitive.  If the signal is high all the time then there will be no valid on request.

    Cherry Zhou said:
    For example, GPIO4 is high when PTPS65941213RWERQ1 is working properly, and then GPIO4 is always high during PTPS65941213RWERQ1 going from active to LP_standby. Then the LP_standby state is also high, will the PMIC go back to active?

    No.  The PMIC will stay in the LP standby state until an edge is seen on the GPIO4.

    An example is described here: https://www.ti.com/lit/ug/slvuc99a/slvuc99a.pdf#page=51

    Regards,
    Chris