AM6526: "MSMC" Memory Access Question

Hello Darren,

To confirm, you are running TI-RTOS on the AM65x A53 core?

Regards,

Nick

Hi Nick,

I am confirming how the S/W is being built, but it is not Linux. 
It would be TI-RTOS or Baremetal based code used in building an application; and that application failing to read the above described registers from the A53 core.

Regards,
Darren

Hi Darren,

Thanks for the additional information. We will be looking into this and try to get back to you next week.

Regards,

Jianzhong 

Hi Jianzhong,

Has there been an update on this topic?
Again, S/W based on the PDK7.3 (Baremetal/RTOS) has been unable to R/W to the following registers from the A53 core.

COMPUTE_CLUSTER0_CPU0 0x0060000000 0x0060FFFFFF 16 MB
COMPUTE_CLUSTER0_CPU1 0x0061000000 0x0061FFFFFF 16 MB
COMPUTE_CLUSTER0_CPU2 0x0062000000 0x0062FFFFFF 16 MB
COMPUTE_CLUSTER0_CPU3 0x0063000000 0x0063FFFFFF 16 MB
COMPUTE_CLUSTER0_CPU4 0x0064000000 0x0064FFFFFF 16 MB
COMPUTE_CLUSTER0_CPU5 0x0065000000 0x0065FFFFFF 16 MB
COMPUTE_CLUSTER0_CPU6 0x0066000000 0x0066FFFFFF 16 MB
COMPUTE_CLUSTER0_CPU7 0x0067000000 0x0067FFFFFF 16 MB
COMPUTE_CLUSTER0_CPU8 0x0068000000 0x0068FFFFFF 16 MB
COMPUTE_CLUSTER0_CPU9 0x0069000000 0x0069FFFFFF 16 MB
COMPUTE_CLUSTER0_CPU10 0x006A000000 0x006AFFFFFF 16 MB
COMPUTE_CLUSTER0_CPU11 0x006B000000 0x006BFFFFFF 16 MB
COMPUTE_CLUSTER0_CPU12 0x006C000000 0x006CFFFFFF 16 MB

Regards,
Darren

Hi Daren,

Sorry for the delayed response, but I haven't been able to find help regarding your inquiry. We have very limited ability in supporting Baremetal/TI-RTOS for A53 on AM65xx. Please refer to the response of this thread.

Regards,

Jianzhong

Sorry to chime in, but the title made me curious, and this might affect us at some point in the future, too.

I believe this is rather a hardware question than a software question. What is behind these addresses? The most specific description of these addresses in the TRM (spruid7e) is in table Table 8-9. MSMC Memory Regions. For 0x60000000 for example is says "MSMC Coherent Interface for CC_ARMSS0". I have no idea if there's anything to be accessed at that address, because afaik if any of the A53's wants to access MSMC (SRAM), it should use 0x70000000.

What is it that your customer actually wants to do?

Regards,

Dominic

Hi Dominic,

I appreciate the follow-up.

Jianzhong, 

I will try and get details on why these address are being written to.
But for now, let's shift away from what S/W for the moment?
From a H/W perspective can you confirm if these registers are firewalled, or in some way blocked from R/W by default, or if they require any specific register R/W sequence to be accessed?

Regards,
Darren

HI Jianzhong, , 

Checking if you have some inputs on the above query ?

Regards,

Sreenivasa

Hi Pekka,

We understand the COMPUTE_CLUSTER_CPUx memory map should have been marked as reserved.
We are worried there are other registers similar to this that cannot be R/W to, but that are not described as such in the TRM.

From "2.1 MAIN Domain Memory Map":

The memory locations not shown in Table 2-1 are either unallocated or reserved and not used. Accesses to these locations are not recommended and should be avoided.

Can you confirm if there are any other addresses listed in Table 2-1 ~ Table 2-6 (all the address space) that are unallocated or reserved, and should not be written to?

Regards,
Darren

In general yes the TRM and specifically the memory map has gone through the release process and reviews, but clearly at least this error got through. The MSMC3 related memory map section does not contain other errors, the way this got through did not let any other errors in. I'd say the error is not necessarily directly the fact the section is there, but that it is not explained what is behind this section. So a description like "COMPUTE_CLUSTER_CPUn : memory region is used to write to L2 or L1 SRAM regions of the connected CPU such as C7x. Reserved memory for Cortex A53 compute clusters. I'm not aware of any other errors.

In general I would broaden and say don't write to sections in the memory map without a reason. Just because there is an area in the memory map does not mean one can write to it. For example the memory map contains areas used for caches of the R5 cores, writing there will have unexpected consequences.

  Pekka