Part Number: SK-AM64
Hi Team,
My customer have concern regarding this device please see details below.
I'm working on a AM64x SK EVM and I would like to get a better understanding of the Inter-Processor Communication. I will need it to exchange messages between two R5F cores running a bare-metal application (no Linux). I already have AM64x MCU+SDK 08.03.00 and I read about IPC_Notify and IPC_RPMessage. What I don't understand is the relation between the HW FIFOs and the IPC Notify API. By looking at the Technical Reference Manual of the AM64x, I read that the IPC provides 8 clusters, 4 users, and a total of 16 mailbox message queues.
On the other hand, by looking at source file "{MCU_PLUS_SDK_INSTALL_DIR}/drivers/ipc_notify/v0/soc/am64x/ipc_notify_v0_cfg.c" I see the 2-dimensional array "gIpcNotifyMailboxConfig", which defines what mailboxes and what HW FIFOs are used, and I don't understand why some HW FIFOs are used more than once. Are there 16 FIFOs per each mailbox or is 16 the maximum number, across all mailboxes? For example, I see that HW FIFO number 1 is used for communication between R5FSS0-1 => R5FSS0-0 but also for A53SS0_0 => R5FSS1-0. How is this possible? It's not quite clear to me what a mailbox is. Is it just a collection of HW FIFOs? Why only mailboxes 0, 2, 4, and 6 are used in "gIpcNotifyMailboxConfig"? Aren't there 8 mailboxes available?
I've already read all the documentation available for IPC Notify (and IPC RPMsg) but it's still not clear to me how everything comes together. I hope you can help me gain a better understanding. I look forward to hearing from you.
Thank you.
Regards,
May
