TDA4VM: When starting the algorithm module, the camera is abnormal

Hi Brijesh,

I will add more details.

1) When the full function(Capture Function + Algorithm Function) is running，it's abnormal

2) When the capture function and the algorithm function (1/2 frequency) are running, it's normal

2) When the capture function is running, it's normal

Schematic diagram：

BR,

Lei

He lei tao,

Are you seeing this issue on TDA4VM device? Also are there any usage of UDMA on A72 algorithm? Wanted to understand what all DMAs are active in the above diagram? 

Regards,

Brijesh

Hi Brijesh,

Are you seeing this issue on TDA4VM device?

==> Yes

Also are there any usage of UDMA on A72 algorithm?

==> It should not be used on the A72.

Wanted to understand what all DMAs are active in the above diagram? 

==> DMA for C66 C71 and CSIRX.

BR，

Lei

Hi Brijesh，

Our camera access method looks like this:

BR,

Lei

Hi Lei,

Since you have all three cameras of same type, can you please try changing one parameter in the CSIRX node? 

Please change the value of tivx_capture_inst_params_t.numPixels to 0x1 and see if there is any change in the output..

Regards,

Brijesh

Hi Brijesh,

I set numPixels to 1 and the problem still occurs

BR，

Lei

Hi Brijesh,

We look forward to your reply.

BR，

Lei

Hi Brijesh，

Sync status：

We confirmed the status of CSIRX, UDMA and DDR bandwidth, and found no abnormality.

BR，

Lei

Hi Brijesh，

In the case of a 3-way camera, the VirtualChannelNum should be 3. But i set VirtualChannelNum to 2 and the problem didn't happen.

Do you have any good comments?

BR，

Lei

hi Lei,

Did not get it. You are using 3 camera input, so virtual channel id for camera should be 0, 1 and 2. Where did you change VirtualChannelNum parameter? 

Regards,

Brijesh

Hi Brijesh,

Cameras are connected through virtual channels 0, 1, and 3.

The modification details are as follows:

--- a/PSDKRA/pdk_jacinto_08_00_00_37/packages/ti/drv/csirx/src/csirx_drv.c
+++ b/PSDKRA/pdk_jacinto_08_00_00_37/packages/ti/drv/csirx/src/csirx_drv.c
@@ -1100,6 +1100,10 @@ static int32_t CsirxDrv_setCslCfgParams(CsirxDrv_CommonObj *captObj,
             Fvid2Utils_memcpy(&strmDataCfgParams,
                           &instObj->cslObj.strmDataCfgParams,
                           sizeof (CSIRX_StreamDataCfg));
+
+            strmDataCfgParams.enableVcSelect = 1U;
+            strmDataCfgParams.vcSelect = 0x7;//3Camera: 0xDU;

BR，

Lei

Hi Brijesh,

Corrected information:

Cameras are connected through virtual channels 0, 1, and 3.

==> Cameras are connected through virtual channels 0, 2, and 3.

BR,

Lei

Hi Brijesh,

When abnormal, data statistics:

Summary of CPU load,
====================

CPU: mpu1_0: TOTAL LOAD =   0. 0 % ( HWI =   0. 0 %, SWI =   0. 0 % )
CPU: mcu2_0: TOTAL LOAD =  38. 0 % ( HWI =   0. 0 %, SWI =   0. 0 % )
CPU: mcu2_1: TOTAL LOAD =   0. 0 % ( HWI =   0. 0 %, SWI =   0. 0 % )
CPU: C66X_1: TOTAL LOAD =   7.58 % ( HWI =   0.18 %, SWI =   0. 4 % )
CPU: C66X_2: TOTAL LOAD =  33.31 % ( HWI =   0.16 %, SWI =   0. 4 % )
CPU:  C7X_1: TOTAL LOAD =  90.30 % ( HWI =   0.18 %, SWI =   0. 2 % )


HWA performance statistics,
===========================

HWA:   VISS: LOAD =  32.38 % ( 186 MP/s )
HWA:   MSC0: LOAD =  31.44 % ( 217 MP/s )


DDR performance statistics,
===========================

DDR: READ  BW: AVG =     67 MB/s, PEAK =     67 MB/s
DDR: WRITE BW: AVG =     29 MB/s, PEAK =     29 MB/s
DDR: TOTAL BW: AVG =     96 MB/s, PEAK =     96 MB/s


Detailed CPU performance/memory statistics,
===========================================

PERF STATS: ERROR: Invalid command (cmd = 00000003, prm_size = 260 B
CPU: mcu2_0: TASK_0:           IPC_RX:   0.21 %
CPU: mcu2_0: TASK_1:       REMOTE_SRV:   0. 0 %
CPU: mcu2_0: TASK_2:        LOAD_TEST:   0. 0 %
CPU: mcu2_0: TASK_3:         TIVX_CPU:   7.97 %
CPU: mcu2_0: TASK_4:          TIVX_NF:   0. 0 %
CPU: mcu2_0: TASK_5:        TIVX_LDC1:   0. 0 %
CPU: mcu2_0: TASK_6:        TIVX_MSC1:   3.47 %
CPU: mcu2_0: TASK_7:        TIVX_MSC2:   0. 0 %
CPU: mcu2_0: TASK_8:       TIVX_VISS1:  11.45 %
CPU: mcu2_0: TASK_9:       TIVX_CAPT1:   1.17 %
CPU: mcu2_0: TASK_10:       TIVX_CAPT2:   0. 0 %
CPU: mcu2_0: TASK_11:       TIVX_DISP1:   1.15 %
CPU: mcu2_0: TASK_12:       TIVX_DISP2:   0. 0 %
CPU: mcu2_0: TASK_13:       TIVX_CSITX:   0. 0 %
CPU: mcu2_0: TASK_14:       TIVX_CAPT3:   0. 0 %
CPU: mcu2_0: TASK_15:       TIVX_CAPT4:   0. 0 %

CPU: mcu2_0: HEAP:   DDR_SHARED_MEM: size =   16777216 B, free =   15749376 B used =    1027840 B( 93 % unused)
CPU: mcu2_0: HEAP:           L3_MEM: size =     262144 B, free =     211968 B used =      50176 B( 80 % unused)
CPU: mcu2_0: HEAP:  DDR_NON_CACHE_M: size =   16777216 B, free =   16776960 B used =        256 B( 99 % unused)

CPU: mcu2_1: TASK_0:           IPC_RX:   0. 0 %
CPU: mcu2_1: TASK_1:       REMOTE_SRV:   0. 0 %
CPU: mcu2_1: TASK_2:        LOAD_TEST:   0. 0 %
CPU: mcu2_1: TASK_3:         TIVX_SDE:   0. 0 %
CPU: mcu2_1: TASK_4:         TIVX_DOF:   0. 0 %
CPU: mcu2_1: TASK_5:      TIVX_MCANR1:   0. 0 %
CPU: mcu2_1: TASK_6:      TIVX_MCANSR:   0. 0 %
CPU: mcu2_1: TASK_7:      TIVX_MCANFR:   0. 0 %
CPU: mcu2_1: TASK_8:      TIVX_MCANSR:   0. 0 %
CPU: mcu2_1: TASK_9:      IPC_TEST_RX:   0. 0 %
CPU: mcu2_1: TASK_10:      IPC_TEST_TX:   0. 0 %
CPU: mcu2_1: TASK_11:      IPC_TEST_TX:   0. 0 %
CPU: mcu2_1: TASK_12:      IPC_TEST_TX:   0. 0 %
CPU: mcu2_1: TASK_13:      IPC_TEST_TX:   0. 0 %
CPU: mcu2_1: TASK_14:      IPC_TEST_TX:   0. 0 %

CPU: mcu2_1: HEAP:   DDR_SHARED_MEM: size =   16777216 B, free =   16773376 B used =       3840 B( 99 % unused)
CPU: mcu2_1: HEAP:           L3_MEM: size =     262144 B, free =     262144 B used =          0 B(100 % unused)
CPU: mcu2_1: HEAP:  DDR_NON_CACHE_M: size =  117440512 B, free =  117440256 B used =        256 B( 26 % unused)

CPU: C66X_1: TASK_0:           IPC_RX:   0. 5 %
CPU: C66X_1: TASK_1:       REMOTE_SRV:   0. 0 %
CPU: C66X_1: TASK_2:        LOAD_TEST:   0. 0 %
CPU: C66X_1: TASK_3:         TIVX_CPU:   7.28 %
CPU: C66X_1: TASK_4:      IPC_TEST_RX:   0. 0 %
CPU: C66X_1: TASK_5:      IPC_TEST_TX:   0. 0 %
CPU: C66X_1: TASK_6:      IPC_TEST_TX:   0. 0 %
CPU: C66X_1: TASK_7:      IPC_TEST_TX:   0. 0 %
CPU: C66X_1: TASK_8:      IPC_TEST_TX:   0. 0 %
CPU: C66X_1: TASK_9:      IPC_TEST_TX:   0. 0 %

CPU: C66X_1: HEAP:   DDR_SHARED_MEM: size =   16777216 B, free =   16757760 B used =      19456 B( 99 % unused)
CPU: C66X_1: HEAP:           L2_MEM: size =     229376 B, free =          0 B used =     229376 B(  0 % unused)
CPU: C66X_1: HEAP:  DDR_SCRATCH_MEM: size =   50331648 B, free =   50331648 B used =          0 B( 14 % unused)

CPU: C66X_2: TASK_0:           IPC_RX:   0. 2 %
CPU: C66X_2: TASK_1:       REMOTE_SRV:   0. 0 %
CPU: C66X_2: TASK_2:        LOAD_TEST:   0. 0 %
CPU: C66X_2: TASK_3:         TIVX_CPU:  33. 5 %
CPU: C66X_2: TASK_4:      IPC_TEST_RX:   0. 0 %
CPU: C66X_2: TASK_5:      IPC_TEST_TX:   0. 0 %
CPU: C66X_2: TASK_6:      IPC_TEST_TX:   0. 0 %
CPU: C66X_2: TASK_7:      IPC_TEST_TX:   0. 0 %
CPU: C66X_2: TASK_8:      IPC_TEST_TX

:   0. 0 %
CPU: C66X_2: TASK_9:      IPC_TEST_TX:   0. 0 %

CPU: C66X_2: HEAP:   DDR_SHARED_MEM: size =   16777216 B, free =   16770048 B used =       7168 B( 99 % unused)
CPU: C66X_2: HEAP:           L2_MEM: size =     229376 B, free =      84980 B used =     144396 B( 37 % unused)
CPU: C66X_2: HEAP:  DDR_SCRATCH_MEM: size =   50331648 B, free =   50331648 B used =          0 B( 14 % unused)

CPU:  C7X_1: TASK_0:           IPC_RX:   0. 7 %
CPU:  C7X_1: TASK_1:       REMOTE_SRV:   0. 0 %
CPU:  C7X_1: TASK_2:        LOAD_TEST:   0. 0 %
CPU:  C7X_1: TASK_3:         TIVX_CPU:  90. 0 %
CPU:  C7X_1: TASK_4:      IPC_TEST_RX:   0. 0 %
CPU:  C7X_1: TASK_5:      IPC_TEST_TX:   0. 0 %
CPU:  C7X_1: TASK_6:      IPC_TEST_TX:   0. 0 %
CPU:  C7X_1: TASK_7:      IPC_TEST_TX:   0. 0 %
CPU:  C7X_1: TASK_8:      IPC_TEST_TX:   0. 0 %
CPU:  C7X_1: TASK_9:      IPC_TEST_TX:   0. 0 %

CPU:  C7X_1: HEAP:   DDR_SHARED_MEM: size =  268435456 B, free =  126177792 B used =  142257664 B( 15 % unused)
CPU:  C7X_1: HEAP:           L3_MEM: size =    8159232 B, free =          0 B used =    8159232 B(  0 % unused)
CPU:  C7X_1: HEAP:           L2_MEM: size =     491520 B, free =     491520 B used =          0 B(100 % unused)
CPU:  C7X_1: HEAP:           L1_MEM: size =      16384 B, free =          0 B used =      16384 B(  0 % unused)
CPU:  C7X_1: HEAP:  DDR_SCRATCH_MEM: size =  268435456 B, free =  260920064 B used =    7515392 B(  1 % unused)

BR，

Lei

Hi Lei,

lei tao said:

+
+            strmDataCfgParams.enableVcSelect = 1U;
+            strmDataCfgParams.vcSelect = 0x7;//3Camera: 0xDU;

but why do you have to change this in the driver? Driver provides SW interface for providing VC number for each channel.. 

i will check where/how vcSelect parameter is used, but ideally you should not need to change the driver. 

Regards,

Brijesh

Hi Brijesh，

We found that strmDataCfgParams is not set. Therefore, the enableVcSelect is 0, so All Virtual Channels are processed.

I suspect the exception is caused by a resource or scheduling problem, but just suspect.

BR，

Lei

Hi Lei,

Can you please revert this change? I think this is not required. We have usecases where we are able to capture 3 camera data without this change. 

This change is not the reason for the issue you are seeing, but does not look correct. 

Again, could you confirm that if you set the number of channels/camera to 2, it works fine? 

Regards,

Brijesh

Hi Brijesh，

The setting of vcSelect is only a test and has been reverted.

When vcSelect = 0x7, the actual number of cameras connected is 2. I checked the change in Frame Queue Count through TIVX_CAPTURE_PRINT_STATISTICS, so I think there is no problem with the evaluation method.

I did the following test again: Based on the software version of the 3-channel camera, the hardware is only connected to the 2-channel camera, and the problem did not occur.

=========================================

The scenarios in which the problem does not occur are organized as follows:

1) Reduce the algorithm running frequency

2) Reduce the number of cameras connected

BR，

Lei

Hi Brijesh，

Supplementary SDK version information：SDK8.0

BR，

Lei

Hi Brijesh,

What are the common resources of CSIRX, VPAC, C66 and C71?

BR，

Lei

Hi Lei,

Well, DMA and DDR are the two important common resources among CSIRX, VPAC, C66 and C7x. but i really there is any conflict. 

Can we do one experiment? Instead of using UDMA channels for CSIRX, can we use DRU channels? 

In order to use UTC channel, please make below changes,

1, In the API CsirxDrv_getDMACfgParams, in the file ti-processor-sdk-rtos-j721e-evm-08_01_00_13\pdk_jacinto_08_01_00_36\packages\ti\drv\csirx\src\csirx_drvUdma.c, change the channel type to UDMA_CH_TYPE_UTC, as shown below.

chType = UDMA_CH_TYPE_UTC;

2, Please add below statement to set the utcid to UTC in the channel params,

chObj->chParams.utcId  = UDMA_UTC_ID_MSMC_DRU0;

3, Please add below statement to setup UTC channel parameters, in the API CsirxDrv_setChUdmaParams. 

{

    Udma_ChUtcPrms          utcPrms;

    /* Intialize UTC channel Paramenters */
    UdmaChUtcPrms_init(&utcPrms);

    utcPrms.chanType = (uint8_t)CSL_UDMAP_CHAN_TYPE_REF_TR_RING;

    /* Configure UTC channel,
    used to configure other channel specific parameters like
    priority, orderid, queue id etc */
    status = Udma_chConfigUtc(&chObj->rxChObj, &utcPrms);
    if(UDMA_SOK != status)
    {
        GT_0trace(VhwaNfTrace, GT_ERR,
                "UDMA UTC channel config failed!!\n");
    }
}

4, since you are using 3 capture channels, you might require to allocate the DRU channels using resource manager. Please refer to below FAQ to allocate DMA channels.

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1097038/faq-tda4vm-workflow-and-resource-allocation-build-flow-for-sysconfig-tool

Regards,

Brijesh

Hi Brijesh,

Please help to answer the following questions with reference to the FAQ：

Lastly, click on Browse button to open existing design for the platform that you are interested in ie PSDKLA/board-support/k3-respart-tool/out/j721s2-evm.syscfg (or j721e-evm.syscfg). Use this as the starting point for any customization.

==>When opening j721e-evm.syscfg, the following error exists, what is the reason?

BR，

Lei

Hi Brijesh,

I tried manually modifying the rm-cfg.c file, to verify, the problem still occurs. rm-cfg.c is modified as follows:

--- a/PSDKLA/board-support/k3-image-gen-2021.05/soc/j721e/evm/rm-cfg.c
+++ b/PSDKLA/board-support/k3-image-gen-2021.05/soc/j721e/evm/rm-cfg.c
@@ -1045,14 +1045,14 @@ const struct boardcfg_rm_local j721e_boardcfg_rm_data = {
                },
                {
                        .start_resource = 168,
-                       .num_resource = 2,
+                       .num_resource = 3,
                        .type = RESASG_UTYPE (J721E_DEV_NAVSS0_RINGACC_0,
                                        RESASG_SUBTYPE_RA_UDMAP_TX_EXT),
                        .host_id = HOST_ID_MAIN_0_R5_0,
                },
                {
-                       .start_resource = 170,
-                       .num_resource = 2,
+                       .start_resource = 169,
+                       .num_resource = 1,
                        .type = RESASG_UTYPE (J721E_DEV_NAVSS0_RINGACC_0,
                                        RESASG_SUBTYPE_RA_UDMAP_TX_EXT),
                        .host_id = HOST_ID_MAIN_0_R5_2,

BR

Lei

Hi Brijesh，

There seems to be a problem with the modification of rm-cfg.c, I will confirm it again.

BR

Lei

Hi Brijesh，

The problem still occurs. rm-cfg.c is modified as follows:

--- a/PSDKLA/board-support/k3-image-gen-2021.05/soc/j721e/evm/rm-cfg.c
+++ b/PSDKLA/board-support/k3-image-gen-2021.05/soc/j721e/evm/rm-cfg.c
@@ -1045,14 +1045,14 @@ const struct boardcfg_rm_local j721e_boardcfg_rm_data = {
                },
                {
                        .start_resource = 168,
-                       .num_resource = 2,
+                       .num_resource = 3,
                        .type = RESASG_UTYPE (J721E_DEV_NAVSS0_RINGACC_0,
                                        RESASG_SUBTYPE_RA_UDMAP_TX_EXT),
                        .host_id = HOST_ID_MAIN_0_R5_0,
                },
                {
-                       .start_resource = 170,
-                       .num_resource = 2,
+                       .start_resource = 171,
+                       .num_resource = 1,
                        .type = RESASG_UTYPE (J721E_DEV_NAVSS0_RINGACC_0,
                                        RESASG_SUBTYPE_RA_UDMAP_TX_EXT),
                        .host_id = HOST_ID_MAIN_0_R5_2,

BR

Lei

Hi Brijesh,

Based on the modification of rm-cfg.c and applying the csirx_drvUdma.c patch,

I found an abnormal Log, please help to confirm?

The abnormal log is as follows:

[MCU2_0]     43.225205 s: src/csirx_drvUdma.c @ Line 329:
[MCU2_0]     43.225248 s: UDMA UTC channel config failed!!

BR

Lei

Hi Lei,

lei tao said:

The problem still occurs. rm-cfg.c is modified as follows:

The changes does not look correct. There should be more changes for channels and rings in this file. 

lei tao said:

[MCU2_0]     43.225205 s: src/csirx_drvUdma.c @ Line 329:
[MCU2_0]     43.225248 s: UDMA UTC channel config failed!!

Is this failing for the newly added ioctl? Because i dont see this error print on the released driver. 

Regards,

Brijesh

Hi Brijesh,

The changes does not look correct. There should be more changes for channels and rings in this file. 

==> Understood, I will try to generate rm-cfg.c by tool.

        Please help with the tool question：Invalid argument '--product'

Is this failing for the newly added ioctl? Because i dont see this error print on the released driver. 

==>Yes.The failure is related to the abnormal configuration of rm-cfg.c?

BR

Lei

Hi Brijesh,

lei tao said:

Please help with the tool question：Invalid argument '--product'

Tool issue resolved.

BR

Lei

ok, please try to reallocate DRU channels from C7x or A72 to mcu2_0 and see if it helps.

Regards,

Brijesh

Hi Brijesh，

What attributes need to be modified for DRU resource adjustment?

MCU2-0 hangs after I adjust "extended Tx channels for DRU Count"，details are as follows:

Brijesh Jadav said:

C7x or A72 to mcu2_0

I can't modify C71 because I don't have C71 code.

BR

Lei

Hi Lei,

Which SDK release are you using ? and which boot flow (SBL or SPL) are you using? 

Regards,

Brijesh

Hi Brijesh，

SDK Version：SDK8.0 PSDKRA+PSDKQA

Boot Flow：SPL

BR,

Lei

Hi Lei,

ok, can you please make DRU channels to 0 for mcu2_1 

Increase DRU channels to 4 for mcu2_0

Generate rm-cfg.c file

and then follow steps (2.a/b/c) mentioned in below link to regenerate board config. Since you are using TDA4VM, the board config will be part of the sysfw.itb file. please replace this generated file in BOOT partition,

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1097038/faq-tda4vm-workflow-and-resource-allocation-build-flow-for-sysconfig-tool/4158091#4158091

Regards,

Brijesh

Hi Brijesh，

Brijesh Jadav said:

then follow steps (2.a/b/c) mentioned in below link to regenerate board config

2.b:

I think Rebuild should be done by the following command: make u-boot && make sysfw-image.

Because rm-cfg.c is compiled to sys.itb by make sysfw-image.

Please help to confirm that my understanding is correct?

BR,

Lei

Hi Lei,

Yup, that's correct.

This FAQ is for TDA4VL. For TDA4VM, sysfw should be rebuild, using "make sysfw" command.

Regards,

Brijesh

Hi Brijesh，

Brijesh Jadav said:

ok, can you please make DRU channels to 0 for mcu2_1 

Increase DRU channels to 4 for mcu2_0

Generate rm-cfg.c file

Build Failed，details are as follows:

BR,

Lei

Hi Lei,

Can you please share full log? I am not able to figure out the exact error in the above log.

Usually if there is any error in the RM, the tool itself will report the error. Do you see any error when generating rm-cfg.c file?

Regards,

Brijesh

Hi Brijesh,

Brijesh Jadav said:

Can you please share full log? I am not able to figure out the exact error in the above log.

[16:46:04]PSDKLA$ make sysfw-image
=====================================
Building the Linux Kernel DTBs
=====================================
make -C /home/tda4/Codes/CICD/sdk8_2_qnx/PSDKLA/board-support/linux-5.10.100+gitAUTOINC+7a7a3af903-g7a7a3af903 ARCH=arm64 CROSS_COMPILE=/home/tda4/Codes/CICD/sdk8_2_qnx/PSDKLA/linux-devkit/sysroots/x86_64-arago-linux/usr/bin/aarch64-none-linux-gnu- tisdk_j7-evm_defconfig
make[1]: 进入目录“/home/tda4/Codes/CICD/sdk8_2_qnx/PSDKLA/board-support/linux-5.10.100+gitAUTOINC+7a7a3af903-g7a7a3af903”
#
# No change to .config
#
make[1]: 离开目录“/home/tda4/Codes/CICD/sdk8_2_qnx/PSDKLA/board-support/linux-5.10.100+gitAUTOINC+7a7a3af903-g7a7a3af903”
make[1]: 进入目录“/home/tda4/Codes/CICD/sdk8_2_qnx/PSDKLA/board-support/linux-5.10.100+gitAUTOINC+7a7a3af903-g7a7a3af903”
make[1]: 离开目录“/home/tda4/Codes/CICD/sdk8_2_qnx/PSDKLA/board-support/linux-5.10.100+gitAUTOINC+7a7a3af903-g7a7a3af903”
make[1]: 进入目录“/home/tda4/Codes/CICD/sdk8_2_qnx/PSDKLA/board-support/linux-5.10.100+gitAUTOINC+7a7a3af903-g7a7a3af903”
make[1]: 离开目录“/home/tda4/Codes/CICD/sdk8_2_qnx/PSDKLA/board-support/linux-5.10.100+gitAUTOINC+7a7a3af903-g7a7a3af903”
make[1]: 进入目录“/home/tda4/Codes/CICD/sdk8_2_qnx/PSDKLA/board-support/linux-5.10.100+gitAUTOINC+7a7a3af903-g7a7a3af903”
make[1]: 离开目录“/home/tda4/Codes/CICD/sdk8_2_qnx/PSDKLA/board-support/linux-5.10.100+gitAUTOINC+7a7a3af903-g7a7a3af903”
make[1]: 进入目录“/home/tda4/Codes/CICD/sdk8_2_qnx/PSDKLA/board-support/linux-5.10.100+gitAUTOINC+7a7a3af903-g7a7a3af903”
make[1]: 离开目录“/home/tda4/Codes/CICD/sdk8_2_qnx/PSDKLA/board-support/linux-5.10.100+gitAUTOINC+7a7a3af903-g7a7a3af903”
make[1]: 进入目录“/home/tda4/Codes/CICD/sdk8_2_qnx/PSDKLA/board-support/linux-5.10.100+gitAUTOINC+7a7a3af903-g7a7a3af903”
make[1]: 离开目录“/home/tda4/Codes/CICD/sdk8_2_qnx/PSDKLA/board-support/linux-5.10.100+gitAUTOINC+7a7a3af903-g7a7a3af903”
make[1]: 进入目录“/home/tda4/Codes/CICD/sdk8_2_qnx/PSDKLA/board-support/linux-5.10.100+gitAUTOINC+7a7a3af903-g7a7a3af903”
make[1]: 离开目录“/home/tda4/Codes/CICD/sdk8_2_qnx/PSDKLA/board-support/linux-5.10.100+gitAUTOINC+7a7a3af903-g7a7a3af903”
make[1]: 进入目录“/home/tda4/Codes/CICD/sdk8_2_qnx/PSDKLA/board-support/linux-5.10.100+gitAUTOINC+7a7a3af903-g7a7a3af903”
make[1]: 离开目录“/home/tda4/Codes/CICD/sdk8_2_qnx/PSDKLA/board-support/linux-5.10.100+gitAUTOINC+7a7a3af903-g7a7a3af903”
make[1]: 进入目录“/home/tda4/Codes/CICD/sdk8_2_qnx/PSDKLA/board-support/linux-5.10.100+gitAUTOINC+7a7a3af903-g7a7a3af903”
make[1]: 离开目录“/home/tda4/Codes/CICD/sdk8_2_qnx/PSDKLA/board-support/linux-5.10.100+gitAUTOINC+7a7a3af903-g7a7a3af903”
make[1]: 进入目录“/home/tda4/Codes/CICD/sdk8_2_qnx/PSDKLA/board-support/linux-5.10.100+gitAUTOINC+7a7a3af903-g7a7a3af903”
make[1]: 离开目录“/home/tda4/Codes/CICD/sdk8_2_qnx/PSDKLA/board-support/linux-5.10.100+gitAUTOINC+7a7a3af903-g7a7a3af903”
make[1]: 进入目录“/home/tda4/Codes/CICD/sdk8_2_qnx/PSDKLA/board-support/linux-5.10.100+gitAUTOINC+7a7a3af903-g7a7a3af903”
make[1]: 离开目录“/home/tda4/Codes/CICD/sdk8_2_qnx/PSDKLA/board-support/linux-5.10.100+gitAUTOINC+7a7a3af903-g7a7a3af903”
=============================
Building SYSFW Image
=============================
make[1]: 进入目录“/home/tda4/Codes/CICD/sdk8_2_qnx/PSDKLA/board-support/k3-image-gen-2022.01”
/home/tda4/Codes/CICD/sdk8_2_qnx/PSDKLA/linux-devkit/sysroots/x86_64-arago-linux/usr/bin/arm-none-linux-gnueabihf-gcc -fno-builtin -Wall -Iinclude/soc/j721e -Isoc/j721e/evm -Iinclude -c -o out/soc/j721e/evm/rm-cfg.o-pre-validated ./soc/j721e/evm/rm-cfg.c
python3 ./scripts/sysfw_boardcfg_validator.py -b out/soc/j721e/evm/rm-cfg.o-pre-validated -i -o out/soc/j721e/evm/rm-cfg.o -s j721e -l out/soc/j721e/evm/rm-cfg.o.log
Makefile:215: recipe for target 'out/soc/j721e/evm/rm-cfg.o' failed
make[1]: *** [out/soc/j721e/evm/rm-cfg.o] Error 1
make[1]: 离开目录“/home/tda4/Codes/CICD/sdk8_2_qnx/PSDKLA/board-support/k3-image-gen-2022.01”
Makefile:173: recipe for target 'sysfw-image' failed
make: *** [sysfw-image] Error 2

Hi Brijesh,

Brijesh Jadav said:

Usually if there is any error in the RM, the tool itself will report the error. Do you see any error when generating rm-cfg.c file?

no errors

BR，

Lei

Hi Lei,

Since the DRU channels has become 0 for one the core, the number of entries should have been reduced, so it would require changes in the soc/j721e/evm/sysfw_img_cfg.h? I see total entries by default are 418, can you please change it to 416 and check it?

Regards,

Brijesh

Something like shown in the attached patch.

/cfs-file/__key/communityserver-discussions-components-files/791/Realloc_5F00_DRU_5F00_Ch.patch

Regards,

Brijesh

Hi Brijesh，

Brijesh Jadav said:

can you please change it to 416 and check it?

Build OK，I will test the function later.

BR,

Lei

Hi Brijesh,

MCU2_ 0 Boot OK, but the image is not captured

BR,

Lei

Hi Lei,

i think mcu2_0 boot is not ok. Can you please run vision_apps_init.sh script and confirm ? 

I think somehow CHRT register of DRU is somehow not accessible on mcu2_0, i am still looking into why it is not accessible.

Regards,

Brijesh

Hi Brijesh，

Brijesh Jadav said:

I think somehow CHRT register of DRU is somehow not accessible on mcu2_0, i am still looking into why it is not accessible.

Try the following changes：

--- a/PSDKLA/board-support/u-boot-2021.01+gitAUTOINC+53e79d0e89-g53e79d0e89/arch/arm/mach-k3/j721e_init.c
+++ b/PSDKLA/board-support/u-boot-2021.01+gitAUTOINC+53e79d0e89-g53e79d0e89/arch/arm/mach-k3/j721e_init.c
@@ -493,7 +493,7 @@ void board_init_f(ulong dummy)
 #ifndef CONFIG_TI_SECURE_DEVICE
                setup_navss_nb();
                setup_c66_qos();
-               setup_main_r5f_qos();
+               //setup_main_r5f_qos();
                setup_vpac_qos();
                setup_dmpac_qos();
                setup_dss_qos();

BR，

Lei

Hi Brijesh，

Brijesh Jadav said:

Can you please run vision_apps_init.sh script and confirm ? 

I get the debug Log through vision_apps_init.sh, and the Ethernet Log is periodically output in the Log. So I think MCU2-0 boot OK.

BR，

Lei

ok, let me check. please confirm if you have enabled DRU channels for CSIRX.

Regards,

Brijesh

Hi Brijesh,

lei tao said:

MCU2_ 0 Boot OK, but the image is not captured

Update Status：

1) Before executing the camera demo, MCU2-0 seems to be normal

2) After executing the camera Demo, MCU2-0 seems to hang up

I suspect that the hang is related to the PDK-8359, can you help confirm:

BR，

Lei

Hi Lei,

But even in this case, the capture should work fine. This API just sets the QOS parameters for R5F, this should not have affected DRU for capture.

Can you please give me some time to recreate this on EVM and check it further?

Regards,

Brijesh

Hi Brijesh，

OK, wait your good news.

BR,

Lei