TDA4VM: veriry the solution for that msmc allocate for a72 cache and c71/mcu sram

Hi,

zhou-lw@reachauto.com said:

1. the SPL/u-boot flow, whether or not allocate msmc for a72 cache and c71/mcu sram together?

You can check if there is any MSMC allocated as Cache for A72 by looking at .msmc_cache_size filed of the j721e_boardcfg_data.msmc in the below file.

<LINUX_SDK_PATH>/board-support/k3-image-gen-2022.01/soc/j721e/evm/board-cfg.c

Default value is 0x0 i.e. all of the MSMC is used by C7x as SRAM.

In TDA4VM (J721E) 8MB of MSMC RAM is present and mapped at 0x7000_0000

128KB from start and 64KB from end is reserved by ATF & DMSC (for IPC) respectively.

Regards

Karan

Karan Saxena said:

The MSMC SRAM is allocated from 0x7000_0000, cache will be allocated from the end.

Example, if you have 3MB Cache configuration then SRAM will be 8MB - 3MB == 5MB starting 0x7000_0000.

thank you very much.  you mean if i have 3M cache and 5M SRAM,

SRAM: start addr is 0x7000_0000,  end addr is 0x704F_FFFF

cache  : start addr is 0x7050_0000  and rest of MSMC

another question, where to set the cache start addr? don't need to set cache range ?will the A72 recognize the range of cache itself?