TDA4VM: SerDes interface level

Cherry Zhou

Part Number: TDA4VM

Hi team,

Here're 2 questions from the customer may need your help:

1) When the SerDes interface of TDA4 is used as SGMII communication, is the differential logic level of the communication CML or LVDS? Or are both able to being supported through s/w configuration?

2) In the case of LVDS, is there a 100 ohm termination match and internal bias inside the chip?

Thanks.

Best Regards,

Cherry

over 3 years ago

0 ShreyasRao over 3 years ago

TI__Guru 62710 points

Hi Cherry,

The TXP/ TXN are each single-ended 50ohm lines. I will have to look into the logic level of the SGMII communication and will let you know.

0 ShreyasRao over 3 years ago

TI__Guru 62710 points

yes, there is 100-ohm on-chip termination and internal bias designed.

The SERDES SGMII logic level is CML and can be configured to LVDS.

refer to Interfacing b/w CML and LVDS - slla120a.pdf

0 xianyang yu over 3 years ago in reply to ShreyasRao

Prodigy 50 points

Could you please provide the document of Interfacing b/w CML and LVDS - slla120a.pdf

0 Cherry Zhou over 3 years ago in reply to ShreyasRao

TI__Mastermind 22235 points

Hi Shreyas,

Thanks for your support and xianyang is the customer I mentioned, you could further discuss on this issue here. Please let me know if any assistance needed.

Thanks and regards,

Cherry

0 ShreyasRao over 3 years ago in reply to xianyang yu

TI__Guru 62710 points

https://www.ti.com/lit/pdf/slla120.

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TDA4VM: SerDes interface level