Hi experts,
I am using J721S2 sdk8.04, the part number of DDR on my board is K4FBE3D4HM-TFCL. I configured serveral arguments on Jacinto7_DDRSS_RegConfigTool and generated dts file to match the chip, but the board boot fail. Please help me to check and fix the issue, thanks very much!
1、Logs show as below:
U-Boot SPL 2021.01-dirty (Aug 15 2022 - 18:45:37 +0800)
SYSFW ABI: 3.1 (firmware rev 0x0016 '22.1.1--v2022.01 (Terrific Llam')
Timeout during frequency handshake
### ERROR ### Please RESET the board ###
2、DDR configures:
