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INTERLEAVE access to DDR

Hi, I'm doing some low level software debug on Netra. And I found the DDR is initialized in INTERLEAVE mode. (xx00h~xx7Fh in EMIF0, xx80h~xxFFh in EMIF1), that means both DDR module 1 and DDR module 2 are used in very early stage. I also notice that DDR can be set as non-interleave mode. Here is the question: Why TI's uboot utilizes INTERLEAVE mode, is there any benifit?

 

Jeff

 

  • Jeff Gu said:
    doing some low level software debug on Netra

    Are you facing any issues in U-Boot loading?

    Jeff Gu said:
    Why TI's uboot utilizes INTERLEAVE mode

    The benefit of DMM interleaving is that the DDR bandwidth is improved by almost a factor of 2

    Regards,

    Vaibhav