• State Resolved
  • Locked Locked
  • Replies 5 replies
  • Subscribers 99 subscribers
  • Views 1462 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

PHY chip detect help with dm365

zanget
Expert 2150 points


we had tried to detect the chip of KSZ8041NL/RNL (MICREL) with no luck in our custom board.

we are tried to read PHY Acknowledge Status Register (ALIVE) in the u-boot but it is always 0 after set MDIO Control Register (CONTROL).

 

(We had set clkdiv , enable , fault , fault_enable bits. for the clkdiv, we had tried with 2.2M, 1M ,respectively )

this source code is form ti dvsdk 4.0 and it works fine with the emv borad.

we also tried to read the device ID of the PHY chip from USERACCESS0 but there is just 0 form that regiest  even if the detect if failed.

this is what we get form the oscilloscope:

 

the datasheet said that :

 The Management Data Input/Output (MDIO) module continuously polls all 32 MDIO addresses in order to
enumerate all PHY devices in the system.

 is it's signal suitable?

any help will appreciate.

regards, Mike

  • 0
    Genius 3925 points

    in include/configs/davinci_dm365evm.h, make sure

    #define CONFIG_EMAC_MDIO_PHY_NUM 

    matches your board configuration. the evm uses 0 while the ipnc uses 1.

  • 0 in reply to Hongfeng Wang
    Expert 2150 points

    it is almost no help untill we changed  to use MDC = 500Hz and we can read the interface/register of PHY chip successfully.

     we are just  using one PHY chip.

    after send the ARP (broadcast) (by using ping command in uboot) to the host  which have a sniffer installed, the host replay to the PHY, we also can detect the signal form the PHY to dm365 in the rx pins by oscilloscope.

     and .. now the problem is that :

    the buffer continuate keep with eth_rx start status = 0x20000000,and the flag : 0xff00 of rx:

    "The status of the buffer is allways equal to EMAC_CPPI_OWNERSHIP_BIT, on every buffer received".

    see here .

    we had tried to use RXINTSTATRAW = 1 and 0 respectively ,but.. still no hope.

    the ping still failed with timeout.

    the commad continuely send 2 ARP (broadcast) package to the host.

    wang, thinks for your responsed.

    regards, mike.

  • 0 in reply to zanget
    Expert 2150 points

    we had solved this problem. see the pic below:

    the green (ch2, the rx pins) get very high when it is in low level. about 0.6V and i think dm365 doesnot support such a high - low level input.

    after we tried with an other batch of this chip (same version:22,1512) it works.

    regards, Mike

  • 0 in reply to zanget
    Expert 2150 points

    it is also strange that if we use the chip of previous batch, after reset by hardware( by the powersupply directly), it is read of addr = 1.

    but now we change to use the gpio to reset the phy, we found that after reset by gpio ,the phy is read as addr = 0

    it puzzles me a lot.

    and now it works fine, although.

  • 0 in reply to zanget
    Prodigy 20 points

    because of the phy that you configured as a  broadcast  addr, so you will read addr = 0 back.