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TDA4VM: DMSC3 - Memory ECC

TS L
Intellectual 911 points
Part Number: TDA4VM

Hi TI Expert,

following picture is from SDL package file“SDL_J721E_diagnostic_mapping.xlsx”

DMSC is running on M3 core ,that means it is running before mcu1_0 running.

1st Queston:

 is "DMSC3 - Memory ECC" implemented by SDL which running on MCU1_0?

or

"DMSC3 - Memory ECC" is done by hardware automatically? that is "DMSC3 - Memory ECC" is enabled by hardware automatically,not enabled by SW?

2nd Question:

there are several ECCs,

which is enabled by hardware automatically?

which is enabled by software?

where i can get this information? which manual？

  • 0
    TI__Guru** 121171 points

    Hi,

    ECC is a hardware diagnostic, which supports software readable status of ECC errors (single and double-bit) and associated info such as RAM
    address and data bit or bits that are in error.   SDL on MCU1_0 would detect/poll ECC errors from DMSC memories.

    The SDL implementation at documentation at SDL_RLS_01.00.00/sdl/sdl_docs/userguide/j721e/modules/ecc.html, and SDL_RLS_01.00.00/sdl/sdl_docs/userguide/j721e/examples/ecc.html, can be referenced for what is required at S/W level to enable ECC.

    Regards,

    kb