Other Parts Discussed in Thread: TLV320AIC3104
Hi,
Our customer is developing with AM4378 using TI-LinuxSDK (v7.03.0.005).
They are using AudioCodec (TLV320AIC3104) and they have confirmed that they can output 44.1kHz audio data with the following dts when MCLK is 24MHz.
< device tree > sound0: sound0 { compatible = "simple-audio-card"; simple-audio-card,name = "TEST"; simple-audio-card,widgets = "Line", "Line Out"; simple-audio-card,routing = "Line Out", "LLOUT", "Line Out", "RLOUT"; simple-audio-card,format = "i2s"; simple-audio-card,bitclock-master = <&sound0_master>; simple-audio-card,frame-master = <&sound0_master>; simple-audio-card,cpu { sound-dai = <&mcasp1>; system-clock-frequency = <24000000>; }; sound0_master: simple-audio-card,codec { sound-dai = <&tlv320aic3104>; system-clock-frequency = <24000000>; }; }; &i2c2 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&i2c2_pins>; tlv320aic3104: tlv320aic3104@18 { #sound-dai-cells = <0>; compatible = "ti,tlv320aic3104"; reg = <0x18>; status = "okay"; reset-gpios = <&gpio5 19 GPIO_ACTIVE_LOW>; IOVDD-supply = <&dummy_vcodec_vdd>; AVDD-supply = <&dummy_vcodec_vdd>; DRVDD-supply = <&dummy_vcodec_vdd>; DVDD-supply = <&vldo1>; }; }; &mcasp1 { #sound-dai-cells = <0>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&mcasp1_pins>; pinctrl-1 = <&mcasp1_sleep_pins>; status = "okay"; op-mode = <0>; tdm-slots = <2>; serial-dir = < 0 1 0 0 >; tx-num-evt = <32>; rx-num-evt = <32>; };
They are trying to change the MCLK of the AudioCodec to 12 MHz (output is 44.1 kHz).
They want to do it from DeviceTree for now, CLKOUT1SEL0DIV (bit[21-20]) in the PRCM_CM_CLKOUT1_CTRL register to set the PRCM output to 12MHz.
They add assigned-clocks, assigned-clock-parents, and assigned-clock-rates to the tlv320aic3104 property in the device tree and
They tried to set the OSC clock (24MHz) to 1/2 the OSC clock (12MHz).
tlv320aic3104: tlv320aic3104@18 { #sound-dai-cells = <0>; compatible = "ti,tlv320aic3104"; reg = <0x18>; status = "okay"; assigned-clocks = <&clkout1_mux_ck>; <-- Add assigned-clock-parents = <&clkout1_osc_div_ck>; <-- Add assigned-clock-rates = <12000000>; <-- Add reset-gpios = <&gpio5 19 GPIO_ACTIVE_LOW>; IOVDD-supply = <&dummy_vcodec_vdd>; AVDD-supply = <&dummy_vcodec_vdd>; DRVDD-supply = <&dummy_vcodec_vdd>; DVDD-supply = <&vldo1>; };
They assumed that with this modification they could set CLKOUT1SEL0DIV (bit[21-20]) in the PRCM_CM_CLKOUT1_CTRL register to b01, but it remained at its default value (b00).
Is there a mistake in the setting position or content?
Best Regards,
Kouji Nishigata