Other Parts Discussed in Thread: SYSCONFIG
In my application, I have IPC working between the ARM and the DSP. However, I infrequently see the ARM's mbox INT handler called when I don't expect it.
In my INT handler, I read the Mailbox IRQSTATUS_0 register and check the NEWMSGENABLEUUMB1 (bit 2). If true, I read the # messages and then each message. If false, I consider this a spurious interrupt. In this case, I report the value of the IRQSTATUS_0 and IRQ_ENABLE_0/1 registers. In either case, I write the value reported by IRQSTATUS_0 back to IRQSTATUS_0 to ack the INT.
Spurious interrupts are happening infrequently. In each case, the status register reports 0xaaa, which suggests that the INT handler was invoked due to the NOTFULLSTATUSUUMB[0/1]. However, I have configured the IRQENABLE registers to only enable the NEWMSGENABLE interrupts. In the INT handler, I dump the state of these registers, and IRQENABLE_0 reads 4 and IRQENABLE_1 reads 1, as I'd expect.
Any ideas for understanding the source of the interrupt?
Here are more details about how I configure the mailbox.
- During init, I set bit 1 (softreset) of MAILBOX_SYSCONFIG.
- Then, I wait for SYSSTATUS[1] to report true.
- Then, I write SYSCONFIG[4:3] to 2 and SYSCONFIG[0] to 1 (auto/smart idle).
- I write 1 to IRQENABLE_0 and 4 to IRQENABLE_1.
Thanks,
-Matt