DRA829V: watchdog

Hi,

If you have access to the Software Diagnostics Library (SDL)  from TI, there is an example therein, which shows setting RTI_WWDSIZECTRL to 100%.    The test runs to completion as below, where RTI_WWDSIZECTRL is being set to 0x5 (100%).

Regards,

kb

Hello KB,

Here is the detailed information, would you help analysis the issue?

To be specific, we are using Module Instance RTI0, which belongs to Main Domain (NOT MCU_RTI0 of MCU Domain).

 Below is the register dump when RTI_WWDSIZECTRL is set to 50%, which will trigger a reset in 5-10s(the watchdog is set to 10 seconds.) after we slay process 2(wdtkick-j7 -d 0),

RTI Register Map, base=0x02200000:

Offset 0x0 ~ 0x88:   0x00000000

Offset 0x90:   0xa98559da

Offset 0x94:   0x00000027

Offset 0x98:   0x00000000

Offset 0x9c:   0x0000a35c

Offset 0xa0:   0x00029686 keeps changing,

Offset 0xa4:   0x0000000a

Offset 0xa8:   0x00000050

Offset 0xac:   0x05050505

Offset 0xb0 ~ 0xbc:   0x00000000

When RTI_WWDSIZECTRL is set to 100%, it will not trigger a reset after we slay process 2(wdtkick-j7 -d 0), by the way, when Window Size is set to 100% wdtkick-j7 writes to RTI_WDKEY every second (we modified the source wdtkick-j7 to make it behave this way).

When wdtkick-j7 is still running, the registers are like this:

RTI Register Map, base=0x02200000:

Offset 0x0 ~ 0x88:   0x00000000

Offset 0x90:   0xa98559da

Offset 0x94:   0x00000027

Offset 0x98:   0x00000000

Offset 0x9c:   0x0000a35c

Offset 0xa0:   0x00049eeb

Offset 0xa4:   0x0000000a

Offset 0xa8:   0x00000005

Offset 0xac:   0x05050505

Offset 0xb0 ~ 0xbc:   0x00000000

And after wdtkick-j7 is killed, RTI_DOWNCOUNTER decreases to 0 and is reloaded to 0x01ffffff and decreases again, and RTI_WDSTATUS is set to 0x32(indicating “DWD timeout period has expired” and “A time-window violation has occurred”). But no reset is triggered.

Hi,

The reset itself is dependent on the handling of the interrupt generated by the watchdog.  The RTI_WDSTATUS bits being at 0x32 would seem to indicate that the watchdog is working and an interrupt should have been generated.

For MAIN RTI0 the outputs on a violation, are interrupts to GIC and ESM.

In the case of the 50% RTI0, you had indicated a reset occurred, were any changes made to SDK S/W to handle the RTI0 interrupt?  

Have you tried running the 100% RTI0 test, immediately after a power cycle, without first testing the 50% RTI0.

Regards,

kb

The design is, SOC_SAFETY_ERRORN is connected to a GPIO input of a PMIC and the PMIC_RESET_N is connected to MCU_PORz/PORz, There is no special code to deal with RTI0 interrupt, just code to set RTI0 registers to set and enable DWWD. I did tried 100% Window size on RTI0 as you recommended, it won't cause a reset for 100% window size.

And we got information from QNX(which provides the software code for DWWD) saying that 100% window size is not supported. So I am a little confused about this.

Hi,

Sorry for no response on this thread. Can you please confirm if you still need help here?

Regards

Karan

No, thanks for asking.

I accept the saying that a 100% window size is not supported.