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TDA4VM: How to insure data consistency in cache?

Lan W
Prodigy 160 points

Part Number: TDA4VM

We deploy one autosar system on main cores(include mcu2_0/mcu2_1/mcu3_0/mcu3_1) with one set of BSW, and to schedule tasks in the different core(execute instructions, read and write data).

There are many tasks of CAN or Eth to handle, but we found there is a lot of CAN or Eth data lost due to data is not behandled in time.

Now we want to use cache to improve the code execution efficiency for multicore autosar system to fix the above data handle issue .

Could you please confirm how to use cache(I-CACHE/D-CACHE/TCM/SRAM) to help on this issue? (We want to use D-cache, but it will lead data in-consistency)

How to avoid cache in-consistency of a multicore autosar system?

  • 0
    TI__Guru* 78145 points

    Hi,

    Lan W said:
    Could you please confirm how to use cache(I-CACHE/D-CACHE/TCM/SRAM) to help on this issue? (We want to use D-cache, but it will lead data in-consistency)

    For Cache you need to configure the MPU for the R5F. See example here - csl/arch/r5/src/startup/startup.c.

    For TCM and SRAM you need to modify the linker file for your application to use the TCMs and SRAM. The addresses are mentioned in the TRM section 2.1 MAIN Domain Memory Map. Also, this can be referenced from the existing linker files from the SDK.

    Lan W said:
    How to avoid cache in-consistency of a multicore autosar system?

    To avoid inconsistency,

    1. You can carve our a small section in the DDR which you keep as un-cached and this you can use to share messages without worrying about data inconsistency.

    Or

    2. If the sharing of data is synchronized, then you can use explicit Cache WB and Invalidate operations before you access data from the other core.

    Regards

    Karan