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DRA829V: QSGMII

Mari Tsunoda
Expert 5726 points
Part Number: DRA829V
Other Parts Discussed in Thread: DRA829

Hi Team,

I received a question from my customer regarding the QSGMII pins. Which of the following combinations is the correct pin combination they should use? Also, are there any restrictions such that it will prevent other pin usage?

  1. SERDES0_TX0_P/SGMII1_TXP0, SERDES0_TX0_N/SGMII1_TXN0, SERDES0_RX0_P/SGMII1_RXP0, SERDES0_RX0_N/SGMII1_RXN0
  2. SERDES0_TX1_P/SGMII2_TXP0, SERDES0_TX1_N/SGMII2_TXN0, SERDES0_RX1_P/SGMII2_RXP0, SERDES0_RX1_N/SGMII2_RXN0
  3. SERDES1_TX0_P/SGMII3_TXP0, SERDES1_TX0_N/SGMII3_TXN0, SERDES1_RX0_P/SGMII3_RXP0, SERDES1_RX0_N/SGMII3_RXN0
  4. SERDES1_TX1_P/SGMII4_TXP0, SERDES1_TX1_N/SGMII4_TXN0, SERDES1_RX1_P/SGMII4_RXP0, SERDES1_RX1_N/SGMII4_RXN0

Also in the datasheet(SPRSP35J)p1, it says "Up to two QSGMII", so their understanding is that there are 2 channels. However, in the TRM(SPRUIL1C)p1874, it seems from Table 12-259 and Table 12-260 that there are 4 channels like the ones above.

Also the EVM uses the combination #2 above correct? They will be using a different SERDES, so they presume they will use combination #4, and have no plans of using #1 and #2. If they connect it as SGMII, will there be no issues? In the QSGMII Specification Revision 1.3, EDCS-540123, it says that QSGMII is defined as four SGMII interleaved with a single link with a 4-channel selector and 2-bit free counter, but they are concerned that using one QSGMII may not function as a SGMII x4ch.

Best regards,

Mari Tsunoda

  • 0
    TI__Guru 62240 points

    Hi Mari,

    The QSGMII is Quad SGMII( combines 4 SGMII with 1.25GBaud resulting in 5G Baud speed QSGMII).

    The DRA829 has four 2-Lane Serdes and one 4Lane Serdes.

    All 4-Lanes in the 4-L Serdes support QSGMII

    and 2 of the four 2-L Serdes support QSGMII.

  • 0 in reply to ShreyasRao
    TI__Guru 62240 points

    There are 2 QSGMII modules in the CPSW9G and they can be used on any SERDES lanes.

    and hence any SERDES lanes can configure the QSGMII modules and the other lanes will be the subordinate lanes for the QSGMII modules.