TDA4VM-Q1: Power Supply Reference Design for TDA4VM

Hi，E2E

   How about this question，thank you

Hi，E2E

   How about this question，thanks

The initial J721E EVM PDN scheme is no longer recommended for new designs since the CPU peak load current while supporting max processing resources over full temp can exceed the 2-phase buck configuration’s max load current capability. All new J721E (DRA829/TDA4VM) product designs should use either the 3-Ph Dual Leo PMIC PDN-0C or 3-Ph Leo + Hera PMIC PDN-1A schemes as described in the “Jacinto 7 J721E Power Solutions” slide set.

Folder path & file - Jacinto7 Product Series/J721E/AppNote/Jacinto7 J721E Pwr Sols:

US - https://cdds.ext.ti.com/ematrix/common/emxNavigator.jsp?objectId=28670.42872.43295.55377&latestRevision=true

The detailed PDN-0C diagram is used for SCH capture. In addition, the detailed PDN system timing diagram was used to capture new PMIC PN that supports this recommended PDN-0C scheme. Please notice that the VDD_IO_1V8 power rail supplied by PMIC LDO3 is connected to SoC's VDDS_MMC0 input supply. The enabling & disabling of this power rail complies with Errata item i2144 to correct eMMC interface issue.

Folder path & file - Jacinto7 Product Series/J721E/AppNote/ DRA829_TDA4VM_3Ph_Dual_Leo_PDN-0C:

US - https://cdds.ext.ti.com/ematrix/common/emxNavigator.jsp?objectId=28670.42872.65023.28220&latestRevision=true

The TDA4VM Starter Kit board (PROC112A(001)_SCH) available on TI website at: SK-TDA4VM Evaluation board | TI.com) uses a PDN-0C variant (no FuSa support) but the power resource & GPIO mapping connections are very closely aligned to PDN-0C.

Thank you for your apply.