TMDS64GPEVM: DDR4 initialization

Pim, this check is performed to ensure the DDR training has completed.  This should run to completion on the EVM.  Ensure you have the latest Sitara Device Support package in CCS:

Go to Help->Code Composer Studio->Installation Details 

Select Sitara Device Support and choose Update.  The latest version should show up as v1.6.1

If you still have failures after this update, please post the complete console output.

Regards,

James

Hello James, 

Sitara Device Support is version 1.6.1. The console output:

CortexA53_0: GEL Output: --->>> DDR4 Initialization is in progress ... <<<---
CortexA53_0: GEL Output: --->>> ECC Disabled <<<---
CortexA53_0: GEL Output: --->>> DDR controller programming in progress.. <<<---
CortexA53_0: GEL Output: --->>> DDR controller programming completed... <<<---
CortexA53_0: GEL Output: --->>> DDR PI programming in progress.. <<<---
CortexA53_0: GEL Output: --->>> DDR PI programming completed... <<<---
CortexA53_0: GEL Output: --->>> DDR PHY Data Slice 0 programming in progress.. <<<---
CortexA53_0: GEL Output: --->>> DDR PHY Data Slice 0 programming completed... <<<---
CortexA53_0: GEL Output: --->>> DDR PHY Data Slice 1 programming in progress.. <<<---
CortexA53_0: GEL Output: --->>> DDR PHY Data Slice 1 programming completed... <<<---
CortexA53_0: GEL Output: --->>> DDR PHY Address Slice 0 programming in progress.. <<<---
CortexA53_0: GEL Output: --->>> DDR PHY Data Slice 2 programming completed... <<<---
CortexA53_0: GEL Output: --->>> DDR PHY Address Slice 1 programming in progress.. <<<---
CortexA53_0: GEL Output: --->>> DDR PHY Address Slice 1 programming completed... <<<---
CortexA53_0: GEL Output: --->>> DDR PHY Address slice 2 programming in progress.. <<<---
CortexA53_0: GEL Output: --->>> DDR PHY Address Slice 2 programming completed... <<<---
CortexA53_0: GEL Output: --->>> DDR PHY programming in progress.. <<<---
CortexA53_0: GEL Output: --->>> Set PHY registers for all FSPs simultaneously (multicast)... <<<---
CortexA53_0: GEL Output: --->>> DDR PHY programming completed... <<<---
CortexA53_0: GEL Output: Debugging enabled
CortexA53_0: GEL Output: Setting MAIN_PLL12_HSDIV0_CLKOUT_400MHz
CortexA53_0: GEL Output: hsdiv_value: 3
CortexA53_0: GEL Output: HSDIV reset asserted
CortexA53_0: GEL Output: HSDIV divider value programmed.
CortexA53_0: GEL Output: HSDIV reset de-asserted
CortexA53_0: GEL Output: MAIN_PLL12_HSDIV0_CLKOUT set.
CortexA53_0: GEL Output: Setting DDR4 frequency...
CortexA53_0: GEL Output: Triggering start bit from PI...
CortexA53_0: GEL Output: --->>> DDR PI initialization started... <<<---
CortexA53_0: GEL Output: Triggering start bit from CTL...
CortexA53_0: GEL Output: --->>> DDR CTL initialization started... <<<---
CortexA53_0: GEL Output: Polling PI DONE bit...
CortexA53_0: GEL Output: pi_int_status = 0x29C12001...
CortexA53_0: GEL Output: - PI_INIT_DONE_BIT set: The power-on initialization training in PI has been completed.
CortexA53_0: GEL Output: - PI_LVL_DONE_BIT set: The leveling operation has completed.
CortexA53_0: GEL Output: - PI_DLL_LOCK_STATE_CHANGE_BIT set: A state change has been detected on the dfi_init_complete signal after initialization.
CortexA53_0: GEL Output: - PI_RDLVL_GATE_DONE_BIT set: A read leveling gate training operation has been completed.
CortexA53_0: GEL Output: - PI_RDLVL_DONE_BIT set: A read leveling operation has been completed.
CortexA53_0: GEL Output: - PI_WRLVL_DONE_BIT set: A write leveling operation has been completed.
CortexA53_0: GEL Output: - PI_VREF_DONE_BIT set: A VREF setting operation has been completed.
CortexA53_0: GEL Output: - Not documented bit set.
CortexA53_0: GEL Output: ctl_int_status = 0x00000008...
 

Kind regards,

Pim

Hi Pim, thanks for the output.  You did not show the any of the PSC/PLL initialization in the console. 

Can you detail the steps you are performing?  There may be a missing step.  Also ensure that there is no SD card installed in the EVM.  

Regards,

James

Hello James, 

Thanks for your suggestion, I removed the SD card, changed the boot selection to NO_BOOT and used the load_dmsc.js script to do the initialization. Now the DDR4 initialization does finish as it should.

But shouldn't booting from the SD behave the same? Doesn't the bootloader on the SD card do the same initialization of PSC's and PLL's as this script?