AM625: How to setup 166 MHz clock speed for OSPI

Hello TI expert,

Do you have any update?

This is waveform from my board 

With OSPI interface, there are three initial stage (tiboot3, uboot, kernel). What is the ospi clock in DDR mode? 

Does the SDK support the 166MHz ospi clock? How to check on Linux?

This is spec of NOR

I saw the dts of u-boot and kernel the max-ospi clock is 25MHz that means the maximum ospi clock will reach to 25MHz in DTR mode.

Thanks

Brian

Hi 

The expert assigned to this is out of office for the next 2 days so please expect delays in response 

Regards

Mukul 

Hi Thinh,

Based on the email you sent to Rahul on the same topic, I assume you use Linux.

The "assigned-clock-rates" property defined in opsi0 node in k3-am62-main.dtsi is the input clock to the OSPI module, while "spi-max-frequency" property defined in the ospi0 -> flash@0 node in k3-am625-sk.dtsi is the OSPI output clock to drive the Flash device.

So if you want the OSPI to drive the Flash device up to 166MHz, you can set "spi-max-frequency" to 166MHz.

Hello Bin,

Did you test the spi-max-frequency to 166MHz on evm board?

I tried to test with 166MHz, 50MHz, the u-boot and kernel driver always read the wrong ID.

Another point that is SBL supports OSPI 50MHz. Is it right? 

Thanks,

Brian

Hi Thinh,

No I didn't test spi-max-frequency to 166MHz on the evm.

Thinh Nguyen said:

I tried to test with 166MHz, 50MHz, the u-boot and kernel driver always read the wrong ID.

You don't need to use Sysconfig tool. What you need is modify kernel device tree k3-am625-evm.dts to change spi-max-frequency to 166MHz and rebuild the kernel dtb.

Thinh Nguyen said:

Another point that is SBL supports OSPI 50MHz. Is it right? 

I am not sure, I only support Linux. MCU+ SDK support is on another team. But based on the Sysconfig screenshot you provided, you refer to OSPI input clock to 50MHz, isn't it? This is not directly related to the OSPI output clock. I feel you mixed both OSPI input and output clocks.

Hello Bin,

Bin Liu said:

You don't need to use Sysconfig tool. What you need is modify kernel device tree k3-am625-evm.dts to change spi-max-frequency to 166MHz and rebuild the kernel dtb.

YES, I known. I only change the "spi-max-frequency" in the device tree "k3-am625-evm.dts" of uboot/kernel. Both 50000000 and 166000000. The AM625 OSPI could not read the ID of NOR exactly. Please verify this case on your side.

Bin Liu said:

I am not sure, I only support Linux. MCU+ SDK support is on another team. But based on the Sysconfig screenshot you provided, you refer to OSPI input clock to 50MHz, isn't it? This is not directly related to the OSPI output clock. I feel you mixed both OSPI input and output clocks.

You did not understand my question. I mean that is The OSPI output clock is 50MHz because the input clock frequency = 200000000 and the input clock divider = 4. (Output OSPI clock = 200000000 / 4 = 50MHz).

If mcu_plus_sdk_am62x_08_03_00_12/ SBL-nor-linux has already support the Output ospi clock 50MHz, why the R5 SPL and kernel on linux sdk could not work with 50MHz?????

What is the MAX output OSPI clock frequency can support on AM625? Do you have plan to verify the MAX output OSPI clock frequency on your EVM?

Thans,

Brian

Hi Brian,

After consulted with our Linux SW Dev team, you would have to follow the procedure described in "PHY calibration" section in https://software-dl.ti.com/processor-sdk-linux/esd/AM62X/08_03_00_19/exports/docs/linux/Foundational_Components/U-Boot/UG-QSPI.html to flash the PHY pattern. Then the OSPI output clock will be the same as the input clock (166MHz as defined in k3-am62-main.dtsi assigned-clock-rates).

The DT property spi-max-frequency in k3-am625-sk.dts defines the max frequency for OSPI device enumeration. The flash access speed will be increased to input clock frequency after the enumeration, if the PHY calibration pattern is flashed.

Our Dev team has validated AM625 OSPI output clock 166MHz in U-Boot and kernel.

Hello Bin,

"Phy calibration allows for higher read performance. To enable phy, the phy calibration pattern must be flashed to OSPI at the start of the last erase sector. For the Cypress S28HS512T flash, this lies at the address 0x3fc0000."

Our board used S28HS02GT with 2Gb. Can I keep the pattern address like S28HS512T? Or I have to change the phy pattern address to the last erase sector by changing the device tree of u-boot/ kernel?

partition@3fc0000 {
                label = "ospi.phypattern";
                reg = <0x3fc0000 0x40000>;
            };

change to:

partition@FFC0000 {
                label = "ospi.phypattern";
                reg = <0xFFC0000 0x40000>;
            };

Thanks

Brian

Hi Brian,

I will look into it and get back to you.

Hi Brian,

The U-Boot and kernel drivers look for the device tree label "ospi.phypattern" to get the offset of the PHY calibration pattern, so yes, you can move the pattern address to anywhere on the Flash device by changing the device tree in U-Boot and kernel.

Hello Bin,

Thanks, I will check on my board

Brian

Hello Bin,

Did you test the ospi 166MHz on your AM625 evm board?

If yes, please show me the waveform.

On our my side, the ospi still 20MHz after update PHy-pattern partition.

Thanks,

Brian

Hi Brian,

I tested on the AM625 SK EVM, the uboot boot time including loading kernel image & DTB is about 15% faster. But I am working remotely and don't have the setup to capture waveforms.

I will look into it to see if I can read the OSPI clock from any register.

Hello Bin,

Look our waveform of OSPI:

Thanks

Brian

Hi Brian,

Sorry for my late response.

I used dd command in Linux to check the OSPI read speed before and after flashed the PHY pattern data, which is ~40MB/sec vs 210MB/sec.

# dd if=/dev/mtd5 of=/dev/null bs=48M count=1

It definitely shows the OSPI output clk is not 20MHz after the PHY is calibrated.