Hello,
I am executing on an OMAP-L138 and have run into an apparent issue with the GPIO interrupt handling between the Linux kernel and my DSP application.
My DSP application is built using the following tool versions..
CGT: 6.1.14
DSP/BIOS: 5.41.
DSPLINK: 1.65.00.02
BIOSPSP: 1.30.01
The ARM side kernel is from psp03.20.00.14
The DSP application has registered for a rising edge interrupt using Gpio_regIntHandler() for pins GP0[3] and GP0[4]. We have registered for an interrupt on GP7[10] within an ARM side app running on Linux. Even though no software on the ARM side has intentionally registered for an interrupt of bank 0, it appears the ARM core is clearing the INTSTAT bit for GP0[3] and GP0[4].
I have run a few experiments to try to figure out why this could be. I updated my ISR to only read the INTSTAT register multiple times, cache these results in a temp variable, and then print the results from a task. After many executions, it appears the INTSTAT register is cleared between reads within my ISR (the point that it is cleared varies on each execution). To me, this is impossible for the DSP to do since I am only reading the register and the bit needs to be written to 1 to clear it. So, that leads me to think that the ARM is the culprit.
How is the gpio interrupt handling on the ARM side of the OMAP-L138 configured by default? Is it possible that the Linux kernel on the ARM side is clearing the INTSTAT bits even though we don't want it to? Is there something magical about bank 0 that we should avoid?
Any help would be appreciated!
Thanks,
Steve
