Other Parts Discussed in Thread: SYSCONFIG
I'm having some trouble understanding how to configure interrupts for the A53 cores running Linux (I'm using Processor SDK v8.02.00.23 with the GPEVM). The end goal is to route a PRU IEP Compare event to an interrupt that can be serviced by a Linux kernel module.
After reading many E2E threads and the TRM, this is my current understanding (correct me if wrong):
1. U-Boot SPL will request resources on boot from the DMSC based on the board config compiled by the k3-image-gen utility. These resource requests can be modified by editing the files under k3-image-gen-[version]\soc\am64x\evm including board_cfg.c, pm-cfg.c, rm-cfg.c, etc. But it looks like these config files only request resources but don't actually map any interrupts via interrupt routers (?) In other words, I see the default AM64x resource config (rm-cfg.c) allocates 16 interrupts from CMPEVT_INTERTR0 to A53 cores (Linux) via the following code:
/* This is actually part of .resasg */
.resasg_entries = {
/* Compare event Interrupt Router */
{
.start_resource = 0,
.num_resource = 16,
.type = RESASG_UTYPE (AM64X_DEV_CMP_EVENT_INTROUTER0,
RESASG_SUBTYPE_IR_OUTPUT),
.host_id = HOST_ID_A53_2,
},
But I haven't found a place where any of these interrupts are actually mapped.
2. It looks like the CMPEVT_INTRTR0 interrupt router could be used to map an IEP Compare event to a Linux interrupt. I see that CMPEVT_INTRTR0 has access to IEP Compare inputs and GIC outputs. Presumably the GIC interrupts can be serviced by a custom Linux kernel module. For example input 16 (PRU_ICSSG0_PR1_IEP0_CMP_INTR_REQ_0 from Table 9-91 in TRM rev D page 4694) could be routed to output 0 (GICSS0_spi_IN_48 from Table 10-157 in TRM rev D page 4782) to map the IEP Compare 0 event to the GIC Interrupt 48. This interrupt could be serviced by a kernel module in Linux. But I'm unsure where to set up this mapping (in U-boot? in device tree? an application running in Linux using some API that communicates with DSMC?)
3. If I was running on the R5F or M4 cores, I see that I could use the SciClient API (from MCU+ SDK) to request the DMSC to set up the interrupt routers, including CMPEVT_INTRTR0. For example I see Sciclient_rmIrqSetRaw() is one of the API calls that seems to map interrupts via interrupt routers. This seems like the correct way to set up interrupt routers when NOT using Processor Linux SDK. But again, I'm unsure how this is supposed to be accomplished when using the Processor SDK Linux boot flow.
4. The SciClient API (from MCU+ SDK) appears that it cannot be used from Linux as the DPL drivers only support bare metal and FreeRTOS (?)
Questions
Is my understanding correct?
Is it true that the resource config files compiled using the k3-image-gen utility only allocates interrupts between the various cores, but doesn't actually map any events through the interrupt routers?
What is the correct way to set up the interrupt routers when booting Linux? Is there a way to do this via device tree? (I don't see any interrupt router drivers listed in Processor SDK Linux docs)
Is there a driver similar to SciClient from MCU+ SDK that can be used within Linux to interact with the DMSC?
