Does anyone have any experience or sample code operating a McSPI module in slave mode - receive only using the FIFO configuration? Is there really a requirement for the chip-select pin to be inactive between each word received in this mode? The signals seem to be coming in OK on the cs0, clk, and simo pins but we're reading garbage from the RX register (and sometimes the RX Overflow bit is set in the MCSPI_IRQSTATUS register).
