Hi TI experts,
I have tested again about this issue. Tried to restart the board for more than 50 times, but only reproduce once.
1) CPSW9G with:
ENET_MAC_PORT_4: RGMII, phyAddr = 7
ENET_MAC_PORT_5: RGMII, phyAddr = 5
ENET_MAC_PORT_8: SGMII, phyAddr = 6
2) Board_serdesCfgQsgmii() is not used, we modify the name and some parameters as:
Board_CfgSgmiiSerdes4
static Board_STATUS Board_CfgSgmiiSerdes4(void)
{
CSL_SerdesResult result;
CSL_SerdesLaneEnableStatus laneRetVal = CSL_SERDES_LANE_ENABLE_NO_ERR;
CSL_SerdesLaneEnableParams serdesLane0EnableParams = {0};
memset(&serdesLane0EnableParams, 0, sizeof(serdesLane0EnableParams));
/* SGMII Config */
serdesLane0EnableParams.serdesInstance = (CSL_SerdesInstance)EDP_SERDES_INSTANCE;
serdesLane0EnableParams.baseAddr = CSL_SERDES_10G0_BASE;
serdesLane0EnableParams.refClock = CSL_SERDES_REF_CLOCK_19p2M;
serdesLane0EnableParams.refClkSrc = CSL_SERDES_REF_CLOCK_INT;
serdesLane0EnableParams.linkRate = CSL_SERDES_LINK_RATE_1p25G;
serdesLane0EnableParams.numLanes = 0x4;
serdesLane0EnableParams.laneMask = 0xF;
serdesLane0EnableParams.SSC_mode = CSL_SERDES_NO_SSC;
serdesLane0EnableParams.phyType = CSL_SERDES_PHY_TYPE_SGMII;
serdesLane0EnableParams.operatingMode = CSL_SERDES_FUNCTIONAL_MODE;
serdesLane0EnableParams.phyInstanceNum = SERDES_LANE_SELECT_CPSW;
serdesLane0EnableParams.pcieGenType = CSL_SERDES_PCIE_GEN3;
serdesLane0EnableParams.laneCtrlRate[0] = CSL_SERDES_LANE_FULL_RATE;
serdesLane0EnableParams.loopbackMode[0] = CSL_SERDES_LOOPBACK_DISABLED;
serdesLane0EnableParams.laneCtrlRate[1] = CSL_SERDES_LANE_FULL_RATE;
serdesLane0EnableParams.loopbackMode[1] = CSL_SERDES_LOOPBACK_DISABLED;
CSL_serdesPorReset(serdesLane0EnableParams.baseAddr);
/* Select the IP type, IP instance num, Serdes Lane Number */
CSL_serdesIPSelect(CSL_CTRL_MMR0_CFG0_BASE,
serdesLane0EnableParams.phyType,
serdesLane0EnableParams.phyInstanceNum,
serdesLane0EnableParams.serdesInstance,
3);
result = CSL_serdesRefclkSel(CSL_CTRL_MMR0_CFG0_BASE,
serdesLane0EnableParams.baseAddr,
serdesLane0EnableParams.refClock,
serdesLane0EnableParams.refClkSrc,
serdesLane0EnableParams.serdesInstance,
serdesLane0EnableParams.phyType);
if (result != CSL_SERDES_NO_ERR)
{
return BOARD_FAIL;
}
/* Assert PHY reset and disable all lanes */
CSL_serdesDisablePllAndLanes(serdesLane0EnableParams.baseAddr, serdesLane0EnableParams.numLanes, serdesLane0EnableParams.laneMask);
/* Load the Serdes Config File */
result = CSL_serdesEthernetInit(&serdesLane0EnableParams);
/* Return error if input params are invalid */
if (result != CSL_SERDES_NO_ERR)
{
return BOARD_FAIL;
}
/* Common Lane Enable API for lane enable, pll enable etc */
laneRetVal = CSL_serdesLaneEnable(&serdesLane0EnableParams);
if (laneRetVal != 0)
{
return BOARD_FAIL;
}
return BOARD_SOK;
}( app_ethfw_freertos.c and enet_appboardutils_j721e_evm.c is used)
3) U-boot has not configured the serdes
4) where is stucked: it seems at "SERDES PLL is not locked"
oot@j7-evm:/opt/vision_apps# [MCU2_0] 3.431455 s: CIO: Init ... Done !!! [MCU2_0] 3.431510 s: ### CPU Frequency = 1000000000 Hz [MCU2_0] 3.431541 s: APP: Init ... !!! [MCU2_0] 3.431562 s: SCICLIENT: Init ... !!! [MCU2_0] 3.431765 s: SCICLIENT: DMSC FW version [21.5.0--v2021.05 (Terrific Llam] [MCU2_0] 3.431803 s: SCICLIENT: DMSC FW revision 0x15 [MCU2_0] 3.431828 s: SCICLIENT: DMSC FW ABI revision 3.1 [MCU2_0] 3.431853 s: SCICLIENT: Init ... Done !!! [MCU2_0] 3.431875 s: UDMA: Init ... !!! [MCU2_0] 3.432856 s: UDMA: Init ... Done !!! [MCU2_0] 3.432899 s: MEM: Init ... !!! [MCU2_0] 3.432933 s: MEM: Created heap (DDR_SHARED_MEM, id=0, flags=0x00000004) @ e1000000 of size 16777216 bytes !!! [MCU2_0] 3.432989 s: MEM: Created heap (L3_MEM, id=1, flags=0x00000000) @ 3600000 of size 262144 bytes !!! [MCU2_0] 3.433035 s: MEM: Created heap (DDR_NON_CACHE_ME, id=5, flags=0x00000000) @ d8000000 of size 16777216 bytes !!! [MCU2_0] 3.433080 s: MEM: Init ... Done !!! [MCU2_0] 3.433099 s: IPC: Init ... !!! [MCU2_0] 3.433147 s: IPC: 6 CPUs participating in IPC !!! [MCU2_0] 3.433197 s: IPC: Waiting for HLOS to be ready ... !!! [MCU2_0] 14.468540 s: IPC: HLOS is ready !!! [MCU2_0] 14.473598 s: IPC: Init ... Done !!! [MCU2_0] 14.473649 s: APP: Syncing with 5 CPUs ... !!! [MCU2_0] 15.504496 s: APP: Syncing with 5 CPUs ... Done !!! [MCU2_0] 15.504541 s: REMOTE_SERVICE: Init ... !!! [MCU2_0] 15.505888 s: REMOTE_SERVICE: Init ... Done !!! [MCU2_0] 15.505998 s: ETHFW: Init ... !!! [MCU2_0] 15.512495 s: =====ETHDBG=====EnetBoard_initEthFw: EnetBoard_configTorrentClks [MCU2_0] 15.516719 s: =====ETHDBG=====EnetBoard_configSierra0Clks(serdes0) [MCU2_0] 15.516787 s: =====ETHDBG=====EnetBoard_initEthFw: Board_ethConfigCpsw2g [MCU2_0] 15.516824 s: Enabling clocks! [MCU2_0] 16.017178 s: ===================GPIO reset done===================== [MCU2_0] 16.017453 s: CPSW_9G Test on MAIN NAVSS [MCU2_0] 16.029583 s: =====ETHDBG=====Board_cpsw9gEthConfig(portNum=3, modesel=2) [MCU2_0] 16.029658 s: =====ETHDBG=====EnetBoard_setPhyConfigRgmii::call EnetBoard_setEnetControl [MCU2_0] 16.030164 s: ================+++PHY= 7 ====supported ENETPHY_MAC_MII_RGMII===== [MCU2_0] 16.030241 s: EnetPhy_bindDriver: PHY 7: OUI:000000 Model:00 Ver:00 <-> 'Q2112' : OK [MCU2_0] 16.030325 s: =====ETHDBG=====Board_cpsw9gEthConfig(portNum=4, modesel=2) [MCU2_0] 16.030379 s: =====ETHDBG=====EnetBoard_setPhyConfigRgmii::call EnetBoard_setEnetControl [MCU2_0] 16.030540 s: =====ETHDBG=====Board_cpsw9gEthConfig(portNum=7, modesel=3) [MCU2_0] 16.031032 s: =====ETHDBG=====EnetBoard_setPhyConfigSgmii: Board_serdesCfgSgmii status=0 [MCU2_0] 16.031132 s: CpswMacPort_setSgmiiInterface: MAC 8: SERDES PLL is not locked [MCU2_0] 16.031195 s: CpswMacPort_setSgmiiInterface: MAC 8: Failed to set SGMII interface: -9 [MCU2_0] 16.031240 s: CpswMacPort_open: MAC 8: failed to set Q/SGMII interface: -9 [MCU2_0] 16.031276 s: EnetMod_open: cpsw9g.macport8: Failed to open: -9 [MCU2_0] 16.031312 s: Cpsw_openPortLinkWithPhy: Port 8: Failed to open MAC: -9 [MCU2_0] 16.031351 s: Cpsw_ioctlInternal: Port 8: Failed to open port link: -9 [MCU2_0] 16.031387 s: EnetPer_ioctl: cpsw9g: Failed to do IOCTL cmd 0x01000102: -9 [MCU2_0] 16.031425 s: Enet_ioctl: cpsw9g: IOCTL 0x01000102 failed: -9 [MCU2_0] 16.031452 s: EnetMcm_enablePorts() failed to open MAC port: -9 [MCU2_0] 16.031498 s: EnetMcm_enablePorts failed [MCU2_0] 16.031564 s: Assertion @ Line: 1038 in /home/hl/gitnew/dvpn-poseidon-tda4x-os/vision_firmware/pdk/packages/ti/drv/enet/examples/utils/enet_mcm.c: ENET_SOK == status : failed !!! [MCU2_1] 3.422382 s: CIO: Init ... Done !!! [MCU2_1] 3.422436 s: ### CPU Frequency = 1000000000 Hz [MCU2_1] 3.422467 s: APP: Init ... !!! [MCU2_1] 3.422485 s: SCICLIENT: Init ... !!! [MCU2_1] 3.422690 s: SCICLIENT: DMSC FW version [21.5.0--v2021.05 (Terrific Llam] [MCU2_1] 3.422726 s: SCICLIENT: DMSC FW revision 0x15 [MCU2_1] 3.422749 s: SCICLIENT: DMSC FW ABI revision 3.1
