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pins state during reset

Other Parts Discussed in Thread: AM1808

I have question about I/O pin state during reset.

"3.7.7 Serial Peripheral Interface Modules (SPI)"in datasheet , for example,

there is the following sentence.

"During reset, all of the pins associated with these registers are weakly pulled down."

But "6.4 Reset" in datasheet say that

"All device pins go to a high-impedance state".

 

Which is correct ?