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DRA829V: QSPI Iclk and Errata i2307

Mari Tsunoda
Expert 5726 points
Part Number: DRA829V
Other Parts Discussed in Thread: DRA829,

Hi Team,

My customer sent me these questions below regarding QSPI.

  1. Assuming that they assign QSPI-Flash to MCU_OSPI1_CSn0 and boot from Main MCU, their understanding is that they will bootstrap as below:
    MCU_BOOTMODE=11_0001_0000
    MCU Only = 0 : Normal boot mode
    Primary Boot Mode A = 010 : QSPI boot

    BOOTMODE = 0010_1010
    Port1 = 0 : MCU_OSPI1
    Iclk = 1 : Iclock source internal
    Csel = 0 : MCU_OSPI1_CSn0
    1. Based on the information above, does this mean that Iclk = 0(Iclock source external) is equivalent to using MCU_OSPI1_CLK as input, and therefore using as SPI slave?
    2. If they boot via QSPI-Flash, the DRA829 becomes the master and so Iclk = 1(Iclock source internal) and so Errata i2307 does not apply?
  2. On a separate but related note, on the EVM there is a pin OSPI1_LBCLKO connects to OSPI1_DQS and SPI1_LBCLKO is written as a feature that facilitates timing closure at high speed.
    1. As long as the 0 Ω resistor is near QSPI-Flash is it ok? They are considering 2x QSPI-Flash, so can you tell me if there is a specification as to how many millimeters it needs to be within.
    2. If the MCU_OSPI1_LBCLKO and MCU_OSPI1_DQS pins are required for boot, is it a mistake that MCU_OSPI0_DQS is listed in spruil1c Table 4-19, but MCU_OSPI1_DQS is not listed in Table 4-20?
    3. Is the loopback relevant here different from the loopback mentioned in errata i2307?

Best regards,

Mari Tsunoda

  • 0
    TI__Genius 17086 points

    Per errata Advisory i2307, the Boot ROM only uses "Iclock source internal" mode, regardless of whether Iclk = 0 or Iclk = 1. The LBCLK0 pin is only used in "Iclock source external mode", where the LBCLK0 output is externally looped-back on the board to the DQS pin. Due to i2307, these pins are not used for Boot. These clocking topologies are not related to master/slave operation.

    Regarding the PCB requirements, please see the below table from the datasheet:

    Table 7-91 OSPI Timing Conditions
    PARAMETER MIN MAX UNIT
    INPUT CONDITIONS
    SRI Input slew rate 3.3 V 2 6 V/ns
    All other modes 1 6 V/ns
    OUTPUT CONDITIONS
    CL Output load capacitance All modes 3 10 pF
    PCB CONNECTIVITY REQUIREMENTS
    td(Trace Delay) Propagation delay
    OSPI_CLK trace    		 No Loopback;
    Internal Pad Loopback    		 450 ps
    Propagation delay
    OSPI_LBCLKO trace    		 External Board Loopback 2*L-30(2) 2*L+30(2) ps
    Propagation delay
    OSPI_DQS trace    		 DQS L-30(2) L+30(2) ps
    td(Trace Mismatch Delay) Propagation delay mismatch
    OSPI_D[i:0](1), OSPI_CSn
    relative to OSPI_CLK    		 All modes 60 ps
    (1) i in D[i:0] = 0 to 7 for OSPI0; i in [i:0] = 3 for OSPI1
    (2) L = Propagation delay of OSPI_CLK trace
  • 0 in reply to B.C.
    TI__Expert 5726 points

    Hi Brad,

    Thanks for your response. I saw in another e2e post for a different device that it has to do with timing closures at higher speeds and that LBCLKO is necessary for these high speeds. I'm referring to this post: https://e2e.ti.com/support/processors-group/processors/f/processors-forum/996835/am6411-how-to-handle-bootmode-9-7-pins/3686691#3686691

    Does the reply in this e2e post also apply to the DRA829V?

    Can you also address these two questions in the original post? I'm not sure as to how the table you mentioned relates to the first question below.

    Mari Tsunoda said:
    • As long as the 0 Ω resistor is near QSPI-Flash is it ok? They are considering 2x QSPI-Flash, so can you tell me if there is a specification as to how many millimeters it needs to be within.
    • If the MCU_OSPI1_LBCLKO and MCU_OSPI1_DQS pins are required for boot, is it a mistake that MCU_OSPI0_DQS is listed in spruil1c Table 4-19, but MCU_OSPI1_DQS is not listed in Table 4-20?

    Here are the two tables.

    Best,

    Mari

  • 0 in reply to Mari Tsunoda
    TI__Genius 17086 points

    Yes, the datasheet timings support higher operating speeds when the External Loopback (with LBCLKO pin) is used.

    Please see the datasheet section "OSPI and QSPI Board Design and Layout Guidelines" for details on the PCB routing requirements, including the option tuning resistors.

    The LBCLKO and DQS pins are not used in Boot due to errata i2307.

  • 0 in reply to B.C.
    TI__Expert 5726 points

    Hi Brad,

    Regardless of the fact that it is not used in boot, is there no MCU_OSPI1_DQS and therefore is not listed in table 4-20?

    Best,

    Mari

  • 0 in reply to Mari Tsunoda
    TI__Genius 17086 points

    There is a MCU_OSPI1_DQS pin, per table "OSPI1 Signal Descriptions" in the device datasheet. I don't know why it's not included in Table 4-20. Any particular concern you have, given that the Boot ROM does not use the LBCLKO/DQS pins due to i2307?

  • 0 in reply to B.C.
    TI__Expert 5726 points

    Hi Brad,

    Thanks for your reply. My customers are just curious as to why it wasn't included in the table and are checking to see if it was a typo.

    Best,

    Mari

  • 0 in reply to Mari Tsunoda
    TI__Genius 17086 points

    Yes, I would assume it was left out inadvertently.

  • 0 in reply to B.C.
    TI__Expert 5726 points

    I will let them know! Thanks for your support.

    Best,

    Mari