Hi,
I've EMIF-related question but let me start with the Dual-voltage IO domain to provide some context-clarifying background.
A dual-voltage IO cell likely has the two sets of transistors, each set is dedicated to one power voltage. And there is a voltage comparator that decides which set to use. So the cell can operate either in low (1.8V) or high (3.3V) voltage mode. On power up, as a VDDSHVn voltage ramps up, the comparator switches the cell to the mode, which is appropriate for current power voltage. It's not documented if the mode selection can take place only at power up time or it can occur each time VDDSHVn has changed during the device operation. So I think it's reasonable to assume that should the need arise to change any VDDSHVn voltage back and forth, the only safe way to do so is through power cycling of whole SoC each time. A damaging things like unwanted through currents, etc. can happen inside the device otherwise.
As for the DRAM IOs, they are actually belongs to a triple-voltage domain (1.8/1.5/1.35V). As the EMIF is also of a high-speed domain, the IOs are implemented there within the instances of the Integrated DDR IOs and DLL (IDID) macro. Unlike the Dual-voltage IOs, there is a lot of registers so the software can program the IO's properties (including the type of logic) as desired. Moreover, on power up, the EMIF performs its internal basic initialization procedure automatically, according to TRM. And again, it's not documented if it'll be acceptable to change the VDDS_DDR voltage later.
Generally, it just makes no sense to change it because anyway each DRAM device type requires specific design rules, termination, etc. But there may be similar DRAM subsystem layout in a designs that uses DDR3 and DDR3L parts. It's matter of population. Consider BeagleBone Black as an example. It uses a DDR3L memory that is powered by 1.5V because of cost-optimal PMIC, resulting in sub-optimal wattage figure. In such a designs, it looks like the problem can be fixed by SW. According to the JEDEC standard, a DDR3L device can be switched to 1.35V or 1.5V mode any time when the reset signal is asserted.
Sure for the software it'll be not as simple as to instruct the PMIC to change VDDS_DDR from 1.5V to 1.35V, because EMIF init and training will be subsequently required. But from the HW perspective, please clarify if it's OK for device reliability to change VDDS_DDR voltage range during operation time.
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wbr
