TDA4VM: TDA4 PCIE2 PHY power on failed

Dear Ruijie,

     Which SDK version are you using?

     From the log I can see the PLL is not locked. Please help check the register of Serdes. You can see from 12.2.5.5 in TRM and check the offset of 80h.

sun ruijie said:

PLL lock of lane failed

Dear Jian,

      Could you help check which register can show customer the PLL status? Thanks.

BR

Sikai

hi SiKai，

The SDK version is 0801，the pcie2 Currently configured as gen3 8Gbps, can it be configured as gen2, how to modify it， thanks。

only set the registers GENERATION_SEL=1h，right？

only set the registers GENERATION_SEL=1h，right？

hi jian,

we use the linux sdk 0801, it print the error log

[    2.852025] cdns-sierra-phy 5020000.serdes: PLL lock of lane failed

[    2.852030] phy phy-5020000.serdes.3: phy poweron failed --> -110

[    2.852037] j721e-pcie 2920000.pcie: Failed to init phy

[    2.852120] j721e-pcie: probe of 2920000.pcie failed with error -110

but when use the sdk 0703 , it is ok.

We found it related to this file （drivers/phy/ti/phy-j721e-wiz.c），what is the Differences？

wiz.diff.zip

hi jian，

the serdes2 refclk is internal clk in the sdk 0703 ， but the serdes2 refclk is external clk in sdk0801， right？

Dear Ruijie,

     Could you help check the two registers mentioned? And you can compare them in SDK 8.1 with SDK 7.3 for more information.

jian35385 said:

  - MACRO_ID_REG at 0x05020000, this should be non-zero. Otherwise, the SEDES power domain may not have been turn on yet

  - if power is ON, check PHY_PMA_CMN_CTRL register, at 0x0502e000, this should have either bit 11 or bit 10 set. indicating one of the PLLs locked. PCIe only requires one PLL 

BR

Sikai

hi SIKAI，

in SDK0801, test：

 #./devmem2 0x5020000
/dev/mem opened.
Memory mapped at address 0x3ffa9620000.
Read at address 0x05020000 (0x3ffa9620000): 0x00007364
#./devmem2 0x502e0000
/dev/mem opened.
Memory mapped at address 0x3ffb0f90000.
Read at address 0x502E0000 (0x3ffb0f90000): 0x00000000

in SDK0703, test：

# ./devmem2 0x5020000
/dev/mem opened.
Memory mapped at address 0x3ffa2df0000.
Read at address 0x05020000 (0x3ffa2df0000): 0x00007364
# ./devmem2 0x502e0000
/dev/mem opened.
Memory mapped at address 0x3ff93fe0000.
Read at address 0x502E0000 (0x3ff93fe0000): 0x00000000

sorry，

in SDK0801, test：

 #./devmem2 0x5020000
/dev/mem opened.
Memory mapped at address 0x3ffa9620000.
Read at address 0x05020000 (0x3ffa9620000): 0x00007364
# ./devmem2 0x502e000
/dev/mem opened.
Memory mapped at address 0x3ffb5930000.
Read at address 0x0502E000 (0x3ffb593e000): 0x00003010

in SDK0703, test：

# ./devmem2 0x5020000
/dev/mem opened.
Memory mapped at address 0x3ffa2df0000.
Read at address 0x05020000 (0x3ffa2df0000): 0x00007364
# ./devmem2 0x502e000
/dev/mem opened.
Memory mapped at address 0x3ff8f710000.
Read at address 0x0502E000 (0x3ff8f71e000): 0x00002435

Notes from 10/31:

1. Jian to send dts for 8.01 for internal refclk.

2. Ruijie/Sikai to confirm with current modified 8.01 dts, ensure internal clk is used, by checking register:

    SERDES_RST @0x0502040c, either PLL0 or PLL1 should be set to 1 (for internal refclk.) Bit 28 or 29. Jian not sure which PLL used if both lanes are PCIe. depending on SERDES config. 

Jian

hi jian，

use the current modified 8.01 dts，the registers value is：

./devmem2 0x0502040c
/dev/mem opened.
Memory mapped at address 0x3ff9f850000.
Read at address 0x0502040C (0x3ff9f85040c): 0xB1000000

the bit 29 is 1.

Thanks，

Ruijie Sun

Hi,

As per above conversation, with 8.01 SDK everything is working and PCIe is Up and running.

Closing the thread. If any issue please create a new thread.

Best Regards,
Sudheer

Hi,

As per above conversation, with 8.01 SDK everything is working and PCIe is Up and running.

Closing the thread. If any issue please create a new thread.

Best Regards,
Sudheer