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SRIO SYSTEM RESET

Mehly
Intellectual 920 points

Hi,

i want to trigger a system reset in the C6474 DSP.

How can i generate an doorbell interrupt to SRIO INT#6 with the CSL?

Thanks.

  • 0
    TI__Guru* 84110 points

    Thank you for joining the TI E2E Community. There is a wealth of information available to you in the many E2E Forum postings, plus you can browse through all the formal TI documentation by starting at www.ti.com , and there are also many useful application topics on software and hardware and tools at http://www.tiexpressdsp.com .

    For some specific information that should help you with the C6474 and SRIO, we offer some online training material at http://e2e.ti.com/media/p/36682.aspx . Please take a look at the SRIO training module first to see if it directly addresses your current question, which I trust it will. 

  • 0 in reply to RandyP
    Intellectual 920 points

    Hi,

    i have studied the online training material. And ich saw, that i can trigger the system reset with the Interrupt Controller without SRIO. Is this right?

    I want that all 3 cores start executing code from 0x00800000, after I fill the L2 memory with valid data (SRIO read from external source with running core 0). Is there an easier way without SRIO doorbell?

    Additionally, the  "Advanced Resets" Function under Debug is not available ???

     

  • 0 in reply to Mehly
    TI__Guru* 84110 points

    It is not yet clear to me what you intend to do. Please explain from a system-level what you want to happen with the DSP. Is this for power-on booting of the DSP, and if so which boot mode do you use?

    Mehly said:

    i can trigger the system reset with the Interrupt Controller without SRIO. Is this right?

    Can you point to a document about triggering "the system reset with the Interrupt Controller"? This is not familiar to me.

    Mehly said:

    I want that all 3 cores start executing code from 0x00800000, after I fill the L2 memory with valid data (SRIO read from external source with running core 0). Is there an easier way without SRIO doorbell?

    It appears that you want the DSP Core0 to do SRIO reads from an external source, in other words an SRIO Master boot mode. If so, how do you get the secondary boot loader into the DSP since SRIO Master Boot is not a supported function?

  • 0 in reply to RandyP
    Intellectual 920 points

    Hi,

    thank you very much for your helping support.

    RandyP said:

    Can you point to a document about triggering "the system reset with the Interrupt Controller"? This is not familiar to me.

    I found it in the online training material: (page:9 first line) http://learningmedia.ti.com/public/c6474/C64x_Startup/C6474_Startup.pdf

    " Initiated by Emulation, sRIO, or C64x+ INTC "

    RandyP said:

    It is not yet clear to me what you intend to do. Please explain from a system-level what you want to happen with the DSP. Is this for power-on booting of the DSP, and if so which boot mode do you use?

    Yes this is for power-on-booting ( secondary Bootloader for SRIO Master Boot from an external source).

    RandyP said:

    It appears that you want the DSP Core0 to do SRIO reads from an external source, in other words an SRIO Master boot mode. If so, how do you get the secondary boot loader into the DSP since SRIO Master Boot is not a supported function?

    I boot my own Bootloader from a I2C EEPROM as it is descibed in the DSP Bootloader Users Guide SPRUG24. This Bootloader do SRIO transfer from an external Source to the Internal L2 memory of all 3 cores. This is already working ;-)

    Now, i am at the end of the boot process and will start my multicore DSP-programm.

     

     

  • 0 in reply to Mehly
    TI__Guru* 84110 points

    The I2C bootmode will result in Core0 executing from the BOOTROM to read the sections of program and/or data from the I2C EEPROM and writing those sections to the target locations of the DSP. When all of the EEPROM has been copied into the DSP, Core0 will branch to a location defined in the boot process and Core1 and Core2 will start executing at their local 0x00800000 addresses (if nothing was loaded to those addresses, there will be an IDLE instruction inserted there).

    If I understand correctly from your system, at this point Core0 begins running the secondary bootloader to read from the SRIO to load additional contents of DSP memory. Having successfully completed that process, you now want to start all three cores running.

    The System Reset, in my opinion, is not the way to do this. The System Reset will cause the DSP to repeat the I2C EEPROM Master boot sequence. From what I can tell, you cannot change the boot mode to No Boot, which might result in your desired operation, so the System Reset would not be able to make things work the way you want.

    My recommendation is to take advantage of the fact that all three cores are already running, and now direct them to where you would like them to be. You have already said that you want them to all start at their local 0x00800000. Your choices include:

    1. Let Core1 and Core2 continue executing the IDLE instruction at 0x00800000. Have your I2C bootcode start at 0x00800000 but have the first 8 instructions be IDLE followed by 7 NOPs to fill the first fetch packet (just a safety precaution). But I am not sure how to get them to fall off the IDLEs if they have not configured and enabled any interrupts.
    2. Have the I2C bootcode include a simple test & branch loop that waits until a memory location is changed and then falls out of the loop. Fill the fetch packet with NOPs. You can have the SRIO bootcode entry point be at the next fetch packet address (like 0x00800020). When Core0 is done with the SRIO bootloading, it will write the new value to the tested memory location for each core and they will fall out of the test & branch loop.
    3. If the I2C bootcode can contain enough code, have Core1 and Core2 get I2C bootcode sufficient to prepare their interrupt configurations (IER, INTC.INTMUX, ISTP, GIE) and then go to a safe location for an IDLE while waiting for an IPC interrupt after the SRIO bootloader. When Core0 is finished with the SRIO bootloading, it can then send an IPC interrupt to Core1 and Core2 to get them started. Both cores will branch to the IPC ISR and will return after the IDLE instruction.

    My preference is #2, and you may find other solutions, too.

  • 0 in reply to RandyP
    Intellectual 920 points

    Now it works perfect,

    thanks a lot for your support RandyP ;-)