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C6748 - I2C0

Other Parts Discussed in Thread: TMS320C6748

Hi Champs,

My Customer is facing a problem with the I2C driver.

They have a constrain in there design – sequential I2C operations time must be constant( less than 1 microsecond between I2C operation) below is the customer problem description.   

We are trying to achieve a deterministic I2C write transaction duration from BIOS I2C

Driver on TMS320c6748 DSP to TLV320aic codec.

There are 4 codec channels on two codec ICs connected in a dazy chain. 

If you are writing program without a BIOS using a different I2C driver all is OK

(I2C write transaction duration is constant).

When we try to use this code in the application using the  

BIOS we get a big fluctuations in I2C write transaction duration.

 

1)      In both drivers we are using the TI I2C controller (I2C0).

2)      In the application the code is executed first in the Init Task.

3)      All interrupts were disabled (GIE).

 

 

What is the root cause of this inconstant beaviour?

How can the customer solves this issue?

Regards

Eran

 

  • Hi Eran,

     

    Can you please confirm which BIOS PSP version they are using?. How are they measuring the write transaction duration when using the application with BIOS?.

     

    Is it possible to share the application code they are using?. This will be more helpful in debugging the issue further. 

     

    Thanks & regards,

    Raghavendra

     

  • Hi Raghavendra,

    The Bios version is 5.41.7.24 and the PSP version is pspdrivers_01_30_01.

    They measuring the transaction time with te ECAP register (~7 nano each cycle).

    About the Application - I'm trying to get it but It will be hard.

     

     

    Thanks

    Eran

     

  • Hi Eran,

     

    In which mode are they configuring the I2c?(Polled/Interrupt/DMA) mode?.

    Would it be possible to check the behavior of the sample application provided by the BIOS PSP during write transactions?. just to check if it is constant or fluctuating.

     

    As per my understanding, you are observing the fluctuation in the time taken for subsequent i2c write. Could you mention how much fluctuation it is?

    Other driver which you are using is a low level driver (non -OS) or is it based on some other OS? [Just out of curiosity!!!]

    Secondly, can you please elaborate "All interrupts were disabled (GIE)"?.

     

    Thanks & regards,

    Raghavendra

  • Hi Raghavendra,

    1. The modes is not determine .Does the default is polled. 

    2. The customer will run the sample application.

    3. The fluaction are 10-100 micro.

    4. The non-os drivers are not base on any OS. 

    5. The are doing HWI disable before the transactions + increasing the Priority to the task.

     

    Regards

    Eran

  • Hi Eran,

     

    Would it possible for them to configure I2C in Interrupt/DMA mode and check its behavior?. This will certainly reduce cpu overhead and give better performance than polled mode. And, where are they disabling the HWI?.

     

    Thanks & regards,

    Raghavendra 

  • Hi,

    I will ask the customer to configure the I2C in Interrupt/DMA mode and I will update you.

     

    Thankas

    Eran