DM6437 only use .cmd problem

I am not sure I understand what you are asking. Are you trying to find a way to dynamically tell the linker how much of the L2 will be used as cache based on how your code configures the L2CFG register? If so, this is not possible as the linker does not take any run-time configurations under consideration. You as the system implementer will need to determine how much RAM is available for the linker to work with.

Because i am .cmd files do not use DSP / BIOS generated and there is no set of dynamically and L2CFG, and my .cmd file, there is no set L1 and L2 Cache, now my .cmd file will be L2 set to SRAM, I'd have the default L1Cache do? Default is defined in evmdm6437.gel ? please tell me thanks.

my .cmd file

-l rts64plus.lib
-stack          0x00001000      /* Stack Size */
MEMORY
{
 L2SRAM  : origin = 0x10800000,  len = 0x00020000

 DDR2 : origin = 0x80000000,  len = 0x08000000
}
SECTIONS
{
 .cinit   >  DDR2
 .text   >  L2SRAM
 .stack   >  DDR2
 .bss   >  L2SRAM
 .const   >  L2SRAM
 .data   >  L2SRAM
 .far   >  DDR2
 .switch  >  L2SRAM 
 .sysmem  >  DDR2
 .tables  >  L2SRAM
 .cio   >  L2SRAM
 .external  >  DDR2
}

At reset L2 defaults to all SRAM, i.e. no cache.  So it's ok to define L2SRAM as 128KB in your linker command file provided that you don't make any run-time changes to the L2 cache configuration.  If you plan to modify the cache configuration then you must modify your linker command file accordingly.

There is no requirement that the cache space be listed in the MEMORY part of the linker command file. You will never allocate any of the cache space in the SECTIONS part, so it is not required to be in the MEMORY part.

DSP/BIOS includes the cache space as a convenience to you so you will have a very clear region of memory that you cannot use for allocation, and if you accidentally set your L2SRAM region too large for the cache size you have included, the linker will give you an error message that the two regions overlap.

It is very rare to change cache sizes dynamically, but there are cases where it can be helpful. The most common case I remember people doing was to change the size of a large buffer in memory in exchange for less cache space. 

But the normal way the cache is used is that you decide how much of L2 will be SRAM and how much will be cache, then put those two regions in the MEMORY part of your linker command file with the SRAM starting at the beginning of the physical memory and the cache starting after the SRAM. 

Thank you very much their reply.

I have a general idea how to do SRAM and L2 planning Cache, but I read some documents that the CPU must be done to communicate through the L1 Cache, but I have .cmd file, there is no plan L1 Cache, it would like to ask whether there is an initial L1 Cache size, whether the initial size of the L1P 32kBytes L1D 32kBytes?

This idea is that if I for the DM6437 the initial establishment of DSP / BIOS L1 is such size.

The datasheet and the C64x+ Megamodule Reference Guide contain details on the status of the cache memories at reset and how to use those.

There is online training available that may help you understand better how to use the cache memories. Even though the series is for a different processor, the module "Memory and Cache" will have a lot of information that will apply to the DM6437 C64x+ core. Please go to http://e2e.ti.com/media/p/36682.aspx and look for the Memory and Cache module.