C6474 Cache

Heather Quinn said:

I am wondering if there is ECC protection on the L1 or L2 cache on the C6474?

Someone else can confirm this but I don't believe any of the TI DSPs so far have had ECC protection on internal memories, generally they have been reliable enough to not need ECC by my understanding. I am kind of curious why you would be interested in this, are you working on a safety critical or hostile environment application?

OK, good to know.

My customer will be using them in a neutron-rich radiation environment, so, yes, it's a hostile environment.  :-/

Hi Heather,

The C6474 does have ECC embedded in L2 cache and it also has Parity checking in L1P.

Regards,

Arun

auppu35501 said:

The C6474 does have ECC embedded in L2 cache and it also has Parity checking in L1P.

Thanks for the correction, I did not realize ECC was in there as I saw no mention of it in the datasheet, do you know if it is on any of the other C64x+ based devices or is this something that was added to C6474?

OK...so if I see any errors come out of the L2 cache then it's a multiple bitflip then.  Do you use any bit interleaving techniques in the L2?