FVID_create() fails after CIPS_init()

Is it on DM648 or DM6446 ?

The IP_run_init() returns an error because it cannot allocate channels.

Anyway try to add the attached files to your project and recompile:

- For dm644x: add bios_edma3_drv_sample_dm644x_cfg.c and vicp_edma3_dm644x_cfg.c

- For dm648: add bios_edma3_drv_sample_dm648_cfg.c and vicp_edma3_dm648_cfg.c

This should resolve any DMA channel conflicts as both files make sure that the DSP's channel partition doesn't conflict with VICP's.

Note that bios_edma3_drv_sample_dm64xx_cfg.c overides the implementation of the same file used to build edma3_drv_bios_sample.lib. All source files for the edma3_drv_bios_sample.lib are available in the edma3 lld package at : TI_EDMA3LLD/packages/ti/sdo/edma3/drv/sample. So an alternative to adding  bios_edma3_drv_sample_dm64xx_cfg.c to your project is to replace the original file in TI_EDMA3LLD/packages/ti/sdo/edma3/drv/sample/src/bios_edma3_drv_sample_dm64xx_cfg.c and rebuild the library using the project edma3_drv_bios_dm64xx_sample_lib.pjt in TI_EDMA3LLD/packages/ti/sdo/edma3/drv/sample/build/dm64xx .

The file  vicp_edma3_dm64xx_cfg.c overrides the original implementation in dmcsl64xx_bios.lib but since we are not providing you any source files, you cannot rebuild it so your only alternative is to add it to your project.

Hope this will help you.

Victor

Hi Victor Greetings!!!!

Thanks for you quick response. Sorry i forgot to mention that I am using DM648 for my display application. Victor I used the file you provided but still I am facing the problem of  failing FVID_create().

Here I just want to discuss the nature of my application so we can find the solution. I am using following configuration:-

VP0(Video Port 0) : For Capture  (Only channel A and Channel B is Free) 

VP1 (Video Port 1) : For Capture  (Only channel A and Channel B is Free)

VP2 (Video Port 2) : For Capture  (Only channel A and Channel B is Free)

VP3 (Video Port 3) : For Display (Only channel A and Channel B is Free)

VP4 (Video Port 4) : For Display  (Only channel A and Channel B is Free)

Now   bios_edma3_drv_sample_dm648_cfg.c  which is provided by you only uses port 20 to 37 for DSP which means VP0 to VP2 only and both channels too. Since we are using all the ports for capture and display so the bios_edma3_drv_sample_dm648_cfg.c  provided by you will not work for us and here lies the actual problem of failing of FVID_create().

This thing i verifed by using your sample dispaly application and configuring VP4 as a dispaly port. It didnt work. Apart from using 5 ports we want to use VICP too. Please note that we are using only channel A of all the ports so Channel B is free. Thus we have the channels for the VICP.

Can you please help us in this regard. It will be a great help if you can provide modified   bios_edma3_drv_sample_dm648_cfg.c and vicp_edma3_dm64xx_cfg.c for our configuration.

I hope I have explained all the details. Waiting for a great help form you.

Thanks and Regards

Abhishek Singh

Hi Victor [:)]

Good news is that it worked finally with the new files provided by you. Thanks for a great help. Here i want to know some things also. Can you please tell us that what all members of sampleEdma3GblCfgParams  structure and sampleInstInitConfig are required to be changed according to the demand of application. Though the files provided by you supports all the video port with vicip but still if somebody needs to change the configuration then how can he do it.  Some explanation will help us to make the change by our own. I request you to post some explanation on this thread so people can self debug.

One again thanks a Lot............... 

Regards

Abhishek Singh

We worked quite a lot on VICP of DM648 on a real-time video recording production. We were able to sort out several issues related to EDMA conflicts in addition to the ones explained here. If you need assistance on VICP of DM648, please contact andrew [at] race-technology.com