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TCI6487/8 boot order

Hello,

in the TMS320TCI648x DSP Bootloader User's Guide (SPRUEA7D) in section 5.3.2 it is stated: "At the end of boot, core 0 releases core 1 and 2 out of reset and then core 0 runs from the entry point in the boot table. Core 1 and core 2 run from the base address of their respective L2 RAM, i.e., 0x800000."

Does anyone know if the three cores run at the same time after they are initialized? Or does core 0 run first and then core 1 and 2 (or core 1 and 2 first, and then core 0)? If they don't run at the same time, is there a way to specify some order/sequence in which they should start running?

I need the three cores to either be initialized first, and then start running together at the same time, or, if this is not possible, to make sure that they run in a specified sequence, since some shared resources have to be initialized correctly before they are accessed by other cores.

 

Thanks,

Petar

  • Petar Minev said:

    Does anyone know if the three cores run at the same time after they are initialized? Or does core 0 run first and then core 1 and 2 (or core 1 and 2 first, and then core 0)? If they don't run at the same time, is there a way to specify some order/sequence in which they should start running?

    I need the three cores to either be initialized first, and then start running together at the same time, or, if this is not possible, to make sure that they run in a specified sequence, since some shared resources have to be initialized correctly before they are accessed by other cores.

    There are a variety of ways to synchronize the three cores once they start running. They will all reach their respective entry points at about the same time, but that might not be good enough for you. One method I have used assumes that DDR has been initialized and that there are three words in a row somewhere that can be used as sync flags. Internal memory could also be used. The code I use is

     volatile int *pCommonMem = (int *)0x80000000;  // or whatever address you want, need three words in a row

     // sync all three cores to be starting at the same time
     for ( i = 0; i < 3; i++ ) pCommonMem[i] = 0;  // clear 3 words to make sure they're all 0
     while ( pCommonMem[0]+pCommonMem[1]+pCommonMem[2] != 3 )  // wait until all 3 locations are set to 1
      if ( pCommonMem[CSL_chipReadReg( CSL_CHIP_DNUM )] == 0 )  // if this core's location is 0 initially or because of another core, set it to 1
       pCommonMem[CSL_chipReadReg( CSL_CHIP_DNUM )] = 1;

    Once all three have exited the while loop, they are sync'd within a few clock cycles. You can then use these or any other flags to control the execution of the cores. For example, you could let Core0 start running some initialization code while Core1 and Core2 wait for their pCommonMem[] locations to be set to 0 by Core0.

    You could get fancier by using IPCs or HWSEMs to signal when Core0 is ready for Cores 1 & 2 to run. But any method you use will allow you to control which order the Cores move forward.