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Improve Read from FPGA via EMIFA using EDMA

Francisco Aguilar
Intellectual 380 points
Other Parts Discussed in Thread: TMS320C6455

Hello, could you please help in the following issue? We're configuring EDMA in the TMS320C6455 in order to send/receive data to/from FPGA via EMIFA bus.  We've found a problem in the EDMA configuration when we are trying to read from FPGA. We detect in the time diagram that every 20 cycles, the ADS signal goes high, so the signals CE and OE goes high too. We don't know if there are some type of limit in the DSP performance when we read from FPGA and we use EDMA. Could we optimize the read from FPGA in order to maintain ADS low during the read period from FPGA?

We send you our EDMA configuration and the time diagram in the read period from FPGA.

 

Any suggestion would be very appreciated!

Many Thanks,

Best Regards,

Francisco

 

Our EDMA configuration is shown below:

        EDMA_PARAM5_OPTION    =      0x00102305;

        /*Option configuration
       100000010 0 011 0000 0 1 0 1

        PRIV:            0
        Reserved:         00   
        Privid:            0000
        ITCCHEN:        0
        TCCHEN:            0
        ITCINTEN:        0
        TCINTEN:        1
        RESERVED:        00
        TCC:            000010
        TCCMODE:        0
        FWID:            011
        RESERVED:        0000
        STATIC:            0
        SYNCDIM:        1
        DAM:            0
        SAM:            1
        */
   
        EDMA_PARAM5_SRC        =      EMIFA_FPGA_READ_WRITE;   
        EDMA_PARAM5_BCNT_ACNT =      0x000101FF;      //ACNT = 1FF BCNT = 1
        EDMA_PARAM5_DST                =         (DIR_BEGIN_RX + 8);
        EDMA_PARAM5_DSTBIDX      =    0x00080000;   //DSTBIDX = 8 SRCBIDX = 2
        EDMA_PARAM5_BCNTRLD    =    0x0000FFFF;
        EDMA_PARAM5_DSTCIDX    =    0x00000000;   
        EDMA_PARAM5_RSVD     =        0x00000001;

        EDMA_DCHMAP_35    =         0x000000A0;   //paentry = 5


        /*
        EDMA_DCHMAP_35: 000000000000000000 000000101 00000

        Reserved: 000000000000000000
        paentry:  000000101
        reserved: 00000

        */

        EDMA_ESRH = 0x00000008; //Event 5 activated

}

 

 

 

 

  • 0
    TI__Guru* 84110 points

    I am very disappointed that otherwise great documentation like the EDMA3 User's Guide has misled you on how to program your transfer. This is not your fault, it is ours for not being more clear about the fact that you should never use the FIFO mode with the C6455. That seems simple enough, but instead we go into a lot of detail on what it does when you do use it, but in reality it is a powerful mode that is only used with internal peripherals that implement a special VBUSM addressing mode, and no peripheral in the C6455 implements that mode.

    Even if it does not solve your immediate problem, I want you to clear SAM to 0 and just use the SRCBIDX field to set your addressing index to the value you need.

    Some things in your code are not clear or are not correct or raise questions for me:

    1. You are using ABSync but BCNT=1 so there is no 2nd dimension to the transfer; ASync would give the same result.
    2. Same thing for SRC/DSTBIDX, since BCNT=1 these will not be used.
    3. ACNT=0x01FF is an odd value (pun intended) to choose especially since you specifically set the FWID field to 64-bits (FWID is not used when you quit using FIFO mode).
    4. The comment for SRCBIDX does not match the value being written.
    5. The comment for ESRH may just be a typo. You are actually activating event 35.

    The way you split out all the fields helps a lot when someone else (me) is trying to understand your code. Embarrassingly, I am more likely to look hard at your problem when you make it this easy. But thanks for breaking it all out like this.

    And now the questions:

    1. What EMIFA mode are you using for this FPGA? Since you are using ADS, it must be synchronous. Which mode in particular?
    2. Is it a problem for the FPGA when ADS goes high? Or is the concern because you recognize that you would get better EMIFA bus utilization without the gaps?
    3. Where is DIR_BEGIN_RX? Internal (which one) or external (which EMIF CE space)? Or just what is the actual value?
    4. How fast is your CPUCLK and your EMIF clock(s)?
    5. From a high level, what do you want the transfer to do? For example, a total of N bytes from a fixed FPGA address in M byte-wide reads and then writing the results to X.

     

  • 0 in reply to RandyP
    Intellectual 380 points

    Thank you so much for your answer RandyP! [:)]

    We've tried your suggestions about EDMA3 configuration and we get the same result. We're a bit desperated. Could you please help? Do you know what could we do?

    We answer your questions:

     

    1. What EMIFA mode are you using for this FPGA? Since you are using ADS, it must be synchronous. Which mode in particular?

    Yes, we're using synchronous mode. Our configuration is the following:

    EMIFA_CE4CFG = 0x8000010B  (10000000000000000000000100001011)

    CE_EXT: 0

    R_ENABLE: 1

    W_LTNCY: 00  --> 0 cyle

    R_LTNCY: 10  --> 2 cycles

    SBSIZE:11  --> 64 bits

     

    2. Is it a problem for the FPGA when ADS goes high? Or is the concern because you recognize that you would get better EMIFA bus utilization without the gaps?

    It is not a problem for the FPGA, but we detect that when ADS goes high, OE goes high too and during 2 cycles we can't read from FPGA, so we lose performance in the read process (low speed)

     

    3. Where is DIR_BEGIN_RX? Internal (which one) or external (which EMIF CE space)? Or just what is the actual value?

    DIR_BEGIN_RX is the internal Address in DSP memory in which read FPGA values.


    How fast is your CPUCLK and your EMIF clock(s)?

    EMIF bus is configured for 48 MHz

     

    From a high level, what do you want the transfer to do? For example, a total of N bytes from a fixed FPGA address in M byte-wide reads and then writing the results to X.

    Our application must read 1FF bytes from a fixed FPGA address writing the result in DIR_BEGIN_RX (internal DSP memory)

    Our configuration after changing the parameteres that you explain is the following:

            //channel 35 DMA y PARAM 5 to send

            EDMA_PARAM5_OPTION    =      0x00102200; 


            /*Configurar option

            100000010 0 010 0000 0 0 0 0
            PRIV:            0
            Reserved:         00   
            Privid:            0000
            ITCCHEN:        0
            TCCHEN:            0
            ITCINTEN:        0
            TCINTEN:        1
            RESERVED:        00
            TCC:            000010
            TCCMODE:        0
            FWID:            010
            RESERVED:        0000
            STATIC:            0
            SYNCDIM:        0
            DAM:            0
            SAM:            0
            */
       
            EDMA_PARAM5_SRC        =      EMIFA_FPGA_READ_WRITE;   
            EDMA_PARAM5_BCNT_ACNT = 0x000101FF;      //ACNT = 1FF BCNT = 1
            EDMA_PARAM5_DST =         (DIR_BEGIN_RX + 8);
            EDMA_PARAM5_DSTBIDX    =    0x00000000;   //DSTBIDX = 0 SRCBIDX = 0
            EDMA_PARAM5_BCNTRLD    =    0x0000FFFF;
            EDMA_PARAM5_DSTCIDX    =    0x00000000;   
            EDMA_PARAM5_RSVD =        0x00000001;

            EDMA_DCHMAP_35    =         0x000000A0;   //paentry = 5


            /*
            EDMA_DCHMAP_35: 000000000000000000 000000101 00000

            Reserved: 000000000000000000
            paentry:  000000101
            reserved: 00000

            */

            EDMA_ESRH = 0x00000008; //Event 5 activated

     

    Many thanks,

    Best Regards!

  • 0 in reply to Francisco Aguilar
    TI__Guru* 84110 points

    It is possible that this is an example of how the EDMA and EMIF will operate. Each burst is the size of the Transfer Controller FIFO, if you are using TC0 or TC1.

    My suggestions and questions are:

    • Try using TC2 or TC3 which have larger read FIFOs and see if the bursts get larger. This would confirm that the FIFOSIZE is setting your burst size limit.
    • Refer to table 2-17 on page 67 of spru966 the EDMA3 User's Guide for rules on generating an optimized transfer.
    • Must the total transfer size be 511 bytes rather than 512?
    • Is there a system limitation keeping the EMIF speed at 48 MHz?
    • R_ENABLE=1 means that the SADSn/SREn pin operates as SREn. Is this what you intended?
  • 0 in reply to RandyP
    Intellectual 380 points

    Thank you so much RandyP!

    We've a question, could you please explain how we can configure EDMA registers in order to use TC2 or TC3?

    Many Thanks,

    Best Regards

  • 0 in reply to Francisco Aguilar
    Intellectual 380 points

    Thank so much Randy!! Now EDMA read from FPGA is great and fast. ADS doesn't go high during read process. We've changed TC and we use TC3 now and runs very fast. Thank you so much!!!  Your help has been very very useful!! [:)]

    Thanks a lot!

    Best Regards