Hello Forum,
Results from the TMS320C6746 power consumption spreadsheet indicate that most of the power savings with DVFS are attributable to reducing the clock frequency, rather than reducing CVDD.
This suggests that a TMS320C6746 design could be simplified by eliminating its I2C control over the CVDD supply voltage and just fixing that voltage at 1.3V; and then relying on clock frequency reduction alone to reduce the DSP power consumption.
With this in mind, my questions are:
1/ For a given configuration, the spreadsheet indicates the following:
At VCVDD=1.3V and 456MHz: P_CVDD = 728mW
At VCVDD=1.3V and 100MHz: P_CVDD = 261mW
At VCVDD=1.0V and 100MHz: P_CVDD = 151mW
This suggests that reducing the clock frequency alone decreases the power consumption by 64%, while reducing VCVDD as well only reduces the power consumption by an additional 15%. Does this seem generally reasonable to you?
2/ So, in order to reduce power consumption, is it necessary for the TMS320C6746 to have control over its CVDD voltage and its clock frequency?
3/ Is the TMS320C6746 capable of reducing its power consumption by controlling its clock frequency alone with a fixed CVDD of 1.3V (456MHz version) or 1.2V (375MHz version)?
4/ Can the TMS320C6746 implement its frequency scaling power management algorithms autonomously, without any control interface to its power source?
5/ Section 5.3.1 (Power-On Sequence) of the datasheet indicates that, if voltage scaling is not used, all variable and static core logic supplies can be controlled from the same power supply and powered up together. If this were done for the 456MHz device this would result in CVDD, RVDD, RTC_CVDD, PLL0_VDDA, PLL1_VDDA and USB_CVDD all being powered from a 1.3V supply rail. Is this acceptable for RTC_CVDD, PLL0_VDDA, PLL1_VDDA and USB_CVDD that, from Table 4.2, are 1.2V nominal?
Thanks in advance for your help!
Regards,
Scott