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change bus master priority on-the-fly on C6747

ting li
Prodigy 200 points

hi, in my project using C6747, and I have following work flow of below:

1. an C6747 GPIO pin input generate an interrupt.

2. interrupt sevice start a DMA, which transfer data from EMIFA to L2 RAM, after start DMA, interrupt sevice need to read/write devices's REGS connect at EMIFA.this cause EMIFA access conflict between DSP MDMA and EDMA. after DMA done, an DMA callback function will process the data.

3. so, if I set bus master priority of EDMA TC priority higher than DSP MDMA, the interrupt service(DSP core)will pend until DMA request done. this is not acceptable for latency of other interrupt handling.

if I set  bus master priority of EDMA TC priority equal DSP MDMA,  interrupt service return before DMA request done. but it seems that if there have 2 DMA request transfering  at same time, interrupt service lantency is also unstable.

4. in task level code, I have EMIFA access that not use DMA,  in my project, DMA transfer is critical, must be done in a given time, so I can not set bus master priority of EDMA TC priority lower than DSP MDMA,  that may cause system failure.

because of up reason, I want to change the DSP MDMA / DSP CFG bus master priority on-the-fly , when enter interrupt, boast it's priority to 1, higer than DMA TC's priority(2), and when leave interrupt, restore orginal priority to 2, same as DMA TC's priority.

C6747 data sheets does not have any informations about dynamic change priority.

 will it work ? or there have some potential problems?

help me please,  thanks. 

  • 0
    TI__Guru* 84110 points

    The intended use of the bus priority registers was that they are written during system initialization and not changed dynamically. But I am not aware of anything that would prevent you from doing this in your program.

    You can change the priority levels at any time during the operation of the DSP, but we have no analysis available for telling you how to do this safely or how many cycles it takes for the change to take effect. It may be useful to set the priority level and then insert a delay wait some clock cycles before the next MDMA operation occurs.

    Another option could be to use a different EDMA TC for the DMA transfers from the Interrupt Service Routine. You could have one TC set with priority 2 and another with priority 3, for example.

    Are your concerns about internal bus conflicts theoretical based on your study of the C6747 architecture or are your concerns based on actual timing measurements?

    The bus priority settings do not give exclusive ownership to the highest priority master for the entire duration of a transfer. Internal bus transfers are comprised of a series of bus commands that are accompanied by read or write data. For a very long transfer, there is usually a gap between multiple commands, and during this gap a lower priority bus command can be inserted. The priority scheme dictates which command gets put on the bus when two or more commands are available at the same time, but multiple masters will generally share the bandwidth of a given bus during times of conflict.

    If the conflict problem you describe is based on actual measurements, then there may be a system-level issue that needs to be resolved rather than just changing priority on the fly. But if the problem is based on your very detailed study of the C6747 documentation, my recommendation would be to set the priorities at the beginning and make measurements.