tci6486 / tms320c6472 EMAC problem

Since this is not a publicly available device at the time of this posting, I do not have any documentation links to offer. But I will assume that you have the lastest EMAC User's Guide for the DSP you are using.

Please read section 2.1.4 RGMII Clocking to understand how the clocking is handled and how it interacts with the PHY.

125 KHz does not make sense, but 125 MHz would be correct.

Albert,

I had the simliar problem for tci6486 EMAC0 for RGMII interface. I will recommend you to check PLL2 configuration.

You need to check the PLL2 control register "bit 0" for enable PLL2 after CSL PLL2 control API.

SYSCLOCK13 for PLLDIV1 = 0x8001  // 250MHz for 1000M RGMII

SYSCLOCK14 for PLLDIV2 = 0x8003 //125Mhz for 100M RGMII

SYSCLOCK15 for PLLDIV3 = 0x8063 //5Mhz for 10M RGMII

To whom might concern,

If I sat MACCONTL as RGMIIEN, I got 25Mhz clock at EMAC0 TX clock.

I tried to sent boardcast packet and I could only sent 25 packets out.

After 25 boradcast packets, EMAC0 was crushed.

I tired to set GMIIEN and gigabit in MACCNTL and I could get the TX dtat with 125Mhz TX CLK. (1000Mbps)

If I changed to set only GMIIEN in MACCNTL and I could get the TX data with 25Mhz TX CLK. (100Mbps)

So I guessed I set the PLL2 correctly and it was working. BUT I can NOT run tci6486 EMAC0 for RGMII mode.

Does anyone can help me, please?

HELP ME!! HELP ME!! PLEASE[:S]

Sungyi cheh

Hi

the problem was that the DSP did not receive RGMII RX clock as input and this seem as absolutely needed. It would be interesting to know if there is a way to force the RGMII to run at gigabit speed (e.g. outputting the TX clock) without and external RX clock alive.

Albert

Sungyi,

The MACSEL config pins are really what enables the EMAC mode (MII, GMII, RGMII, etc) and the clocking used.  I'm not sure if the missing RX clock, that Albert mentioned, fixed your problem too, but if you are still having problems generating the 125Mhz TX clock for RGMII 1Gb mode, please send a dump of the EMAC control registers.

Regards,

Travis

Travis,

After I configured PHY as loopback mode, I could get 125Mhz RX clock and RX data in by oscillator.

But I cannot get the any receive data in DSP side.

I checked MACSTAUS and RX relative registers but it did not show any error or receive packet flag.

Could you help me to figure out which register that I should check or what problem is, please?

thank you for your help.

Sungyi

Sungyi,

I'm not sure of your setup, are you using the TCI6486 EVM or your own board?  Also, are you already using the Network Developer's Kit (NDK)?  If not, this is the first thing we recommend to our C64x customers.  The NDK can be downloaded for free at:

http://focus.ti.com/docs/toolsw/folders/print/ndktcpip.html

It covers both intialization and packet example using the MAC.  If you can follow this example, you should be able to get around your current issue.

Regards,

Travis

Sungyi,

You discuss use of the TCI6486 EVM.  Do you have the TCI6486 EVM User's Guide?  It explains the configuration of the EVM hardware so that you can develop code on the TCI6486.  Jumpers on the EVM allow the DSP to be configured for Ethernet Boot mode.  The TMS320TCI648x Bootloader User's Guide describes the packet format and exchange process needed to load a binary image on the DSP.  The Ethernet Bootloader runs from ROM and configures everything needed for Ethernet operation.  You can then reference the TMS320TCI6486 DSP EMAC/MDIO Module User's Guide so that you can use Code Composer Studio to access the EMAC configuration and status registers.  The EMAC User's Guide describes the configuration options that you are seeking.  Do you have access to these documents?

Tom

Tom,

I read the TCI6486 EVM user guide but I can not find the Ethernet boot setting in the document.

I tried to configure EMAC0 PHY by u-boot "ges" command but it did not work.

ges dreg 0x2 0x0-----> reg = 0xffff

ges mreg 0x2 0x2000------> reg = 0xffff

Could you help me for RGMII EMAC0 PHY (88E1143) by u-boot, please?