What am I doing wrong, pars secunda?

Usually an issue like this, where ACPY3_wait returns but DMA has not occurred, has to do with cache issues. Are you sure the SRC/DST addresses are not cached ? And if they are, you are performing the right cache write-back invalidate operations before and after the transfer ?

Also make sure the DMA is enabled for your device.

Gunjan said:

Usually an issue like this, where ACPY3_wait returns but DMA has not occurred, has to do with cache issues.

The shared region cache is enabled.  The point of using DMA is to transfer rows and columns from DDR to L1 and back again, will setting the shared region cacheEnable to false in the .cfg file fix this, or is the issue with the Source and Destination addresses themselves (which may be cached)?

Lee Holeva

I'm not sure what you are using the "shared region" for., so I can't comment on that one.

How do you put the data (rows and colums) in DDR2 ? Are you sure that data is in DDR and not still in cache when you initiate the transfer ? The DEST address should be fine, if that's in L1DSRAM.

Usually if there's something wrong with the DMA setting, the ACPY3_wait blocks and doesn't return. Since, in your case, the wait does return, I suspect some issue with the cache etc.

I tried disabling the shared region cache, but that had no effect, the DMA transfer still did not happen.

Gunjan said:

How do you put the data (rows and colums) in DDR2 ? Are you sure that data is in DDR and not still in cache when you initiate the transfer ?

The host allocates memory for the image, copies the image into shared memory and then sends the shared address via messageQ to the DSP, followed by:

Imgin[k] = SharedRegion_getPtr (srImgin[k]);

to translate the address to the DSP's memory space.  Looking at memory pointed to by imgin[0], I can see the image bytes in memory.  The DMA is initiated by:

 imginPtr = inImg[0];

TransferRowin(DMAHandle[0], imginPtr, &row_inbuf[flip][0], IMAGEROWSIZE);

The bytes at row_inbuf[flip][ ] never change.

Is there a way to tell whether DMA is enabled on the DSP?  The TI81xx EDMA doc says that the DSP should have available QDMA channels 0-3 and 5-7.

Lee Holeva

When you say "looking at the memory pointed to my imgin[0]" what exactly do you mean ? Are you looking at this memory via CCS ? Could you make sure you are looking at an uncached view of the memory locations ?

Also, if you could share some trace, I could look at it and let you know if there's something suspicious there.

I am not disputing whether the QDMA channels assigned to DSP are correct. But I had to add the following to my "gel" file to get any sort of  DMA  to work on TI816X and am wondering if you need to do something similar.

#define PRCM_BASE_ADDR			0x48180000

#define CM_ALWON_L4_SLOW_CLKSTCTRL  (PRCM_BASE_ADDR + 0x1400)

#define CM_ALWON_TPCC_CLKCTRL (PRCM_BASE_ADDR + 0x15F4)
#define CM_ALWON_TPTC0_CLKCTRL (PRCM_BASE_ADDR + 0x15F8)
#define CM_ALWON_TPTC1_CLKCTRL (PRCM_BASE_ADDR + 0x15FC)
#define CM_ALWON_TPTC2_CLKCTRL (PRCM_BASE_ADDR + 0x1600)
#define CM_ALWON_TPTC3_CLKCTRL (PRCM_BASE_ADDR + 0x1604)

hotmenu EDMAEnable()
{
    GEL_TextOut("\tPRCM for EDMA Initialization in Progress \n","Output",1,1,1);
    WR_MEM_32(CM_ALWON_L4_SLOW_CLKSTCTRL, 2); // it was L3
    WR_MEM_32(CM_ALWON_TPCC_CLKCTRL ,   2); 
    WR_MEM_32(CM_ALWON_TPTC0_CLKCTRL ,   2);
    WR_MEM_32(CM_ALWON_TPTC1_CLKCTRL ,   2);
    WR_MEM_32(CM_ALWON_TPTC2_CLKCTRL ,   2);
    WR_MEM_32(CM_ALWON_TPTC3_CLKCTRL ,   2);

    /* Wait for IDLEST to read 0x0 indicating that the module is fully functional */

    while(((RD_MEM_32(CM_ALWON_TPCC_CLKCTRL)&0x30000)>>16)!=0);
    GEL_TextOut("\tPRCM for EDMA Initialization in Done \n","Output",1,1,1);
}

Gunjan said:

When you say "looking at the memory pointed to my imgin[0]" what exactly do you mean ? Are you looking at this memory via CCS ? Could you make sure you are looking at an uncached view of the memory locations ?

In debug view of CCS4.2.3, I type the address of the translated image buffer, imgin[0],  into the memory display window, and I see the bytes change to red after the code runs.  I assume that this is the actual DDR memory.

Gunjan said:

But I had to add the following to my "gel" file to get any sort of  DMA  to work

I'm not using a GEL file to connect to the DSP.

Gunjan said:

Also, if you could share some trace, I could look at it and let you know if there's something suspicious there.

I'm in the process of figuring-out how to setup trace for Framework.  I'm running Framework 3.21.

Lee Holeva

Okay, in the debug memory view, there should be some check boxes that let you check whether you are viewing the contents in memory directly or if they are cached. It would be good to uncheck the boxes, to make sure the memory contents (both src dest) being viewed aren't cached.

Details of how to use trace in FC 3.21 should be the same as the details for 3.20 listed here:-

http://processors.wiki.ti.com/index.php/Trace_in_Framework_Components#Framework_Components_3.20

Gunjan said:

Details of how to use trace in FC 3.21 should be the same as the details for 3.20 listed here:-

http://processors.wiki.ti.com/index.php/Trace_in_Framework_Components#Framework_Components_3.20

How do I set this up for non-algorithm mode? In particular, what do I do with the Log_setup.cfg file?   Is adding it to my existing .cfg file by a xdc.loadCapsule() the correct thing to do?  Is any additional run-time code needed?  I'm not using Codec Engine.

Update:

I attempted to add Log_setup.cfg to my app's cfg file via a loadCapsule(), but xdc complains of not being able to find "ti.sdo.utils.loggers".  Any idea where this might be?

Lee Holeva

Gunjan said:

Okay, in the debug memory view, there should be some check boxes that let you check whether you are viewing the contents in memory directly or if they are cached. It would be good to uncheck the boxes, to make sure the memory contents (both src dest) being viewed aren't cached.

My debug memory display is not identical to yours:

before DMA:

After DMA:

Lee Holeva

There's nothing in the trace-setup description that is specific to Codec Engine or algorithms. 

As described there, you can add the contents of log_setup.cfg directly to your cfg file. The alternative is to import that file, from your current cfg file as follows:-

utils.importFile("./Log_setup.cfg");

The runtime-code you need to add to your application (preferably in your "main()" function) is also listed on that page:-

/* Set default mask for FC modules */
FCSettings_init();
Diags_setMask(FCSETTINGS_MODNAME"+EX1234567");

Regarding the error message you are getting, the ti.sdo.utils.loggers module should be part of your package path, if you have correctly included the osal_1_21_00_05_eng OSAL installtion in your xdc path.

Please double check that.

Ok, I enabled the logging display, and now DMAN3 does not like its configuration:

 The full trace output:

Shared region cache is disabled

[t=0x0000000a:06229ae5] [tid=0x94a3e10c] ti.sdo.fc.dman3: [+E] DMAN3_createChannels> Enter (groupId=0, dmaTab=0x94a55fb8, numChans=2

[t=0x0000000a:062341ad] [tid=0x94a3e10c] ti.sdo.fc.dman3: [+E] checkDMAN3Configuration> Enter

[t=0x0000000a:0623b7c7] [tid=0x94a3e10c] ti.sdo.fc.dman3: [+7] checkDMAN3Configuration> Bad Qdma channel configuration 0x94a47800

[t=0x0000000a:06245ecc] [tid=0x94a3e10c] ti.sdo.fc.dman3: [+7] DMAN3_createChannels> Bad DMAN3 Configuration. Exit (status=DMAN3_EFAIL)

Channel create failed. Status: -2

Here is the Framework part of the .cfg:

var DMAN3 = xdc.useModule('ti.sdo.fc.dman3.DMAN3');
var ACPY3 = xdc.useModule('ti.sdo.fc.acpy3.ACPY3');

/* Note new configuration in DMAN3 */
DMAN3.useExternalRM = false;
//DMAN3.useExternalRM = true;

DMAN3.heapInternal = "L1DHEAP";
DMAN3.heapExternal = "EXTERNALHEAP";

if (DMAN3.useExternalRM == true) {
    var EDMA3 = xdc.useModule("ti.sdo.fc.edma3.Settings");
    EDMA3.semCreateFxn = "mySemCreate";
    EDMA3.semDeleteFxn = "mySemDelete";
    EDMA3.semPendFxn = "mySemPend";
    EDMA3.semPostFxn = "mySemPost";
    EDMA3.persistentAllocFxn = "_ALG_allocMemory";
    EDMA3.persistentFreeFxn = "_ALG_freeMemory";

    var EDMA3LLD = xdc.loadPackage('ti.sdo.edma3.rm');
    EDMA3LLD.profile = "debug";
    EDMA3.maxPaRams = [4,3,2,0,0,5];
    EDMA3.maxTccs = [4,3,2,0,0,5];
    DMAN3.numQdmaChannels = 1;
}
else {
    DMAN3.qdmaPaRamBase = 0x09004000;
    DMAN3.numQdmaChannels = 8;
    DMAN3.paRamBaseIndex = 78;
    DMAN3.numPaRamEntries = 48;
    DMAN3.nullPaRamIndex = 127;
    DMAN3.tccAllocationMaskH = 0xffffffff;
    DMAN3.tccAllocationMaskL = 0x0;
    DMAN3.numTccGroup   = [4, 3, 2, 0, 0, 5];
    DMAN3.numPaRamGroup = [4, 4, 2, 0, 0, 5];
    DMAN3.qdmaChannels = [0, 1, 2, 3, 5, 6, 7];
    DMAN3.maxQdmaChannels = 7;
    DMAN3.maxTCs          = 4;
}

xdc.loadPackage("ti.sdo.fc.global").profile = "debug";

When I ran without logging, DMAN3_createChannels( ) succeeded and gave back handles.

Lee Holeva

Your numQdmaChannels is the number of channels being used by DMAN3, that is actually 7 now, and not 8. 

The maxQdmaChannels should be 8, to indicate that there are 8 channels available on this hardware.

Could you make the above changes ?

Also, the pictures you are attaching are really low resolution, I can't really make out anything from them.

Gunjan said:

The maxQdmaChannels should be 8, to indicate that there are 8 channels available on this hardware.

Could you make the above changes ?

I changed maxQdmaChannels to 8, but the results are the same:

Shared region cache is disabled

[t=0x00000008:7fe38a7f] [tid=0x94a3e10c] ti.sdo.fc.dman3: [+E] DMAN3_createChannels> Enter (groupId=0, dmaTab=0x94a55fb8, numChans=2

[t=0x00000008:7fe430f3] [tid=0x94a3e10c] ti.sdo.fc.dman3: [+E] checkDMAN3Configuration> Enter

[t=0x00000008:7fe4a779] [tid=0x94a3e10c] ti.sdo.fc.dman3: [+7] checkDMAN3Configuration> Bad Qdma channel configuration 0x94a47800

[t=0x00000008:7fe54ec9] [tid=0x94a3e10c] ti.sdo.fc.dman3: [+7] DMAN3_createChannels> Bad DMAN3 Configuration. Exit (status=DMAN3_EFAIL)

Channel create failed. Status: -2

Here is my code to activate channels:

     dmaTab[k].handle = NULL;
     dmaTab[k].numTransfers = 1;
     dmaTab[k].numWaits = 1;
     dmaTab[k].priority = IDMA3_PRIORITY_LOW;
 
     /*
     * The ACPY3 transfer protocol will be used as the IDMA3 protocol object
     * This object defines the memory requirements and the initialization and
     * de-initialization functions for the protocol's environment
    */
     dmaTab[k].protocol = &ACPY3_PROTOCOL;
     dmaTab[k].persistent = FALSE;
   }

    /*
     * On success this call will return a valid DMA channel handle with the
     * attributes defined above
     */
   status = DMAN3_createChannels(0, dmaTab, 2);

    if (status == DMAN3_SOK ) {

        h[0] = dmaTab[0].handle;
 h[1] = dmaTab[1].handle;
     /* Put the channel in active state */
     /* Now other ACPY3 APIs can be called on this handle */
        ACPY3_activate(h[0]);
 ACPY3_activate(h[1]);
    }
    else {

        System_printf("Channel create failed. Status: %d\n", status);
        return(-1);
    }
    return(0);
}

Here is what is actually at 0x94A47800:

Lee Holeva

Per your trace, the configuration isn't right to DMAN3. This happens usually in one of the following use cases:-

1. There is an issue in the configuration

2. There is an error in the base address

3. There is an issue accessing the DMA.

I don't see any obvious issues in the configuration, and I used the same base address for my TI816X experiments. I have seen errors like you see above, in the scenario when the DMA isn't accessible by the DSP (gel file issue, that I keep mentioning over and over). The DSP would end up reading garbage values from the configuration register, so it assumes all configuration is wrong.

One thing you could try for me, is to set a breakpoint in the checkDMAN3Configuration function (where the error occurs), and look at the memory content at the address represented by the global variable _DMAN3_edma3Addr. If you could show the content of the first couple of entries at that address, it would maybe give me a clue about whether you are actually looking at the DMA registers or not !

Gunjan said:

One thing you could try for me, is to set a breakpoint in the checkDMAN3Configuration function (where the error occurs), and look at the memory content at the address represented by the global variable _DMAN3_edma3Addr. If you could show the content of the first couple of entries at that address, it would maybe give me a clue about whether you are actually looking at the DMA registers or not !

Full screen shot:

Detail showing the memory:

Local variables:

Lee Holeva

Thanks for that legwork Lee, per the view of memory at addresses 0x0900 0000 and 0900 0004, it seems like the DMA is accessible at that address. I also confirmed that the number of QDMA channels for this hardware is 8 (per the configuration).

We should be very close to figuring out why we see the failure. Could you simply step-through the checkDMAN3Configuration and see where this function fails. The code is something like:-

 /* Check if qdma channels assigned are all within range */

    for (i = 0; i < DMAN3_PARAMS.numQdmaChannels ; i++) {

        if (DMAN3_PARAMS.qdmaChannels[i] >= numQdma) {

            status = FALSE;

            Log_print1(Diags_ENTRY, "[+7] checkDMAN3Configuration> Bad "

                    "Qdma channel configuration 0x%x\n",

                    DMAN3_PARAMS.qdmaChannels[i]);

            return (FALSE);

        }

    }

Gunjan said:

Could you simply step-through the checkDMAN3Configuration

DMAN3_PARAMS after the failure:

Lee Holeva

I think that we're chasing a phantom. I rebuilt my DSP code without logging and DMAN3 succeeded in giving me a IDMA Handle.  If I build the DSP code with debugging I get build warning from xdc:

warning: xdc.runtime.Diags: "/home/lholeva/ti-ezsdk_dm816x-evm_5_01_01_80/xdctools_3_20_08_88/packages/xdc/runtime/Diags.xs", line 232: ti.sdo.ipc.transports.TransportShmSetup diags_USER7: ti.sdo.ipc.transports.TransportShmSetup.common$.diags_USER7 has been modified from its default. Diags.USER7 has been deprecated and is now equivalent to Diags.INFO. diags_INFO has not been changed from its default, so the value xdc.runtime.Diags.RUNTIME_OFF from USER7 will be used.

In tracing trough, I notice that I cannot set break points in acpy3_start_arm.c, yet I have the acpy3 folder in the target search path.  I can set break points in acpy3_activate( ). This suggests that the acpy_start( ) code is not actually built.  Do I need to define this variable:

xdc_target__isaCompatible_64P ?

In stepping the code I see it going to acpy3_start( ) in acpy3_start.h (executable c code in a header file?).  I stepped into the code there, perhaps this makes sense to you:

Details of the local variables:

Update:

I had a bad log_setup.cfg file.  I switched to that given in the Framework samples and logging works without the build warnings.  Here are some more variables in ACPY3_start( ):

 Only DMAN3 stuff is tracing:

Shared region cache is disabled

[t=0x0000000d:6a6f8677] [tid=0x94a41bec] ti.sdo.fc.dman3: [+E] DMAN3_createChannels> Enter (groupId=0, dmaTab=0x94a59b78, numChans=2

[t=0x0000000d:6a7027e2] [tid=0x94a41bec] ti.sdo.fc.dman3: [+E] checkDMAN3Configuration> Enter

[t=0x0000000d:6a709915] [tid=0x94a41bec] ti.sdo.fc.dman3: [+X] checkDMAN3Configuration> Exit (status=1)

[t=0x0000000d:6a711393] [tid=0x94a41bec] ti.sdo.fc.dman3: [+4] DMAN3_createChannels> Total Qdma channels requested 2, PaRams requested 2, Tccs requested 2

[t=0x0000000d:6a71c5cd] [tid=0x94a41bec] ti.sdo.fc.dman3: [+E] getContext> Enter (pContext=0x94a59b24, groupId=0, nTccs=2, nPaRams=2)

[t=0x0000000d:6a725d8c] [tid=0x94a41bec] ti.sdo.fc.dman3: [+2] getContext> Context exists for groupId 0, context 0x94a535f4

[t=0x0000000d:6a72e8c3] [tid=0x94a41bec] ti.sdo.fc.dman3: [+2] getContext> Creating context for group 0 Tccs 2 PaRams 2

[t=0x0000000d:6a736e87] [tid=0x94a41bec] ti.sdo.fc.dman3: [+E] createContext> Enter (pContext=0x94a59ae4, groupId=0, nTccs=2, nPaRams=2)

[t=0x0000000d:6a74058f] [tid=0x94a41bec] ti.sdo.fc.dman3: [+2] createContext> Allocate memory for the context

[t=0x0000000d:6a74813d] [tid=0x94a41bec] ti.sdo.fc.dman3: [+2] createContext> Allocate 4 tccs

[t=0x0000000d:6a74f3a5] [tid=0x94a41bec] ti.sdo.fc.dman3: [+2] createContext> Next free tcc index 0

[t=0x0000000d:6a75652e] [tid=0x94a41bec] ti.sdo.fc.dman3: [+2] createContext> Allocate 4 paRams

[t=0x0000000d:6a75d8b9] [tid=0x94a41bec] ti.sdo.fc.dman3: [+2] createContext> NextpaRam index 78

[t=0x0000000d:6a764737] [tid=0x94a41bec] ti.sdo.fc.dman3: [+X] createContext> Exit (status=0)

[t=0x0000000d:6a76b587] [tid=0x94a41bec] ti.sdo.fc.dman3: [+X] getContext> Exit (status=DMAN3_SOK)

[t=0x0000000d:6a7726a6] [tid=0x94a41bec] ti.sdo.fc.dman3: [+2] DMAN3_createChannels> Context 0x94a535f4

[t=0x0000000d:6a779f36] [tid=0x94a41bec] ti.sdo.fc.dman3: [+E] createChannels> Enter (context=0x94a535f4, alg=0x0, groupId=0, dmaTab=0x94a59b78, numChans=2)

[t=0x0000000d:6a785651] [tid=0x94a41bec] ti.sdo.fc.dman3: [+2] createChannels> Channel 0

[t=0x0000000d:6a78c1de] [tid=0x94a41bec] ti.sdo.fc.dman3: [+4] createChannels> Env Requested memTab[0]: size=0x40, align=0x20, space=IALG_PERSIST, attrs=IALG_DARAM0

[t=0x0000000d:6a797217] [tid=0x94a41bec] ti.sdo.fc.dman3: [+2] createChannels> Channel 1

[t=0x0000000d:6a79d89b] [tid=0x94a41bec] ti.sdo.fc.dman3: [+4] createChannels> Env Requested memTab[1]: size=0x40, align=0x20, space=IALG_PERSIST, attrs=IALG_DARAM0

[t=0x0000000d:6a7a8bea] [tid=0x94a41bec] ti.sdo.fc.dman3: [+2] createChannels> Creating channel 0, size 0x40, align 0x20, scratchEnv 0x0

[t=0x0000000d:6a7b227a] [tid=0x94a41bec] ti.sdo.fc.dman3: [+4] createChannels> IDMA3 Object Requested mem[0]: size=0x28, align=0x4 heapId=-1801090328

[t=0x0000000d:6a7bce04] [tid=0x94a41bec] ti.sdo.fc.dman3: [+4] createChannels> IDMA3 Object Allocated mem[0]: size=0x28, align=0x4, heapId=-1801090328, base=0x10f00000

[t=0x0000000d:6a7c860f] [tid=0x94a41bec] ti.sdo.fc.dman3: [+2] createChannels> Assigning qdmaChannel 0

[t=0x0000000d:6a7cfa1e] [tid=0x94a41bec] ti.sdo.fc.dman3: [+2] createChannels> Env buffer of size 0x40 requested

[t=0x0000000d:6a7d83ff] [tid=0x94a41bec] ti.sdo.fc.dman3: [+4] createChannels> Env Allocated memTab[0]: size=0x40, align=0x20, heapId=-1801090328, base=0x10f00040

[t=0x0000000d:6a7e37bd] [tid=0x94a41bec] ti.sdo.fc.dman3: [+2] createChannels> Initializing IDMA3_handle

[t=0x0000000d:6a7eb31a] [tid=0x94a41bec] ti.sdo.fc.dman3: [+E] initHandle> Enter (handle=0x10f00000, dmaTab=0x94a59b78, qdmaChannel=0, env=0x10f00040, scratchEnv=0x0, context=0x94a535f4)

[t=0x0000000d:6a7f7fac] [tid=0x94a41bec] ti.sdo.fc.dman3: [+2] initHandle> Initializing IDMA3 handle with 1 tccs, 1 PaRams, qdmaChannel 0, env 0x10f00040

[t=0x0000000d:6a802613] [tid=0x94a41bec] ti.sdo.fc.dman3: [+2] initHandle> Non-zero env handle

[t=0x0000000d:6a809390] [tid=0x94a41bec] ti.sdo.fc.dman3: [+2] initHandle> paRam block 0x90049c0, tcc Table 0x94a53518

[t=0x0000000d:6a8119cc] [tid=0x94a41bec] ti.sdo.fc.dman3: [+2] initHandle> Call protocol Init function

[t=0x0000000d:6a819191] [tid=0x94a41bec] ti.sdo.fc.dman3: [+X] initHandle> Exit (status=1)

[t=0x0000000d:6a81fbf7] [tid=0x94a41bec] ti.sdo.fc.dman3: [+2] createChannels> Assigned Qdma Channel(s):0

[t=0x0000000d:6a8272ba] [tid=0x94a41bec] ti.sdo.fc.dman3: [+2] createChannels> Assigned PaRam(s):

[t=0x0000000d:6a82e172] [tid=0x94a41bec] ti.sdo.fc.dman3: [+2] createChannels> dmaTab[0].handle's paRamAddr 0x90049c0

[t=0x0000000d:6a83657e] [tid=0x94a41bec] ti.sdo.fc.dman3: [+2] createChannels> 78 (Addr 0x90049c0)

[t=0x0000000d:6a83d7a9] [tid=0x94a41bec] ti.sdo.fc.dman3: [+2] createChannels> Assigned Tcc(s):

[t=0x0000000d:6a844567] [tid=0x94a41bec] ti.sdo.fc.dman3: [+2] createChannels> 32

[t=0x0000000d:6a84a616] [tid=0x94a41bec] ti.sdo.fc.dman3: [+2] createChannels> Creating channel 1, size 0x40, align 0x20, scratchEnv 0x0

[t=0x0000000d:6a853a1e] [tid=0x94a41bec] ti.sdo.fc.dman3: [+4] createChannels> IDMA3 Object Requested mem[1]: size=0x28, align=0x4 heapId=-1801090328

[t=0x0000000d:6a85e2b4] [tid=0x94a41bec] ti.sdo.fc.dman3: [+4] createChannels> IDMA3 Object Allocated mem[1]: size=0x28, align=0x4, heapId=-1801090328, base=0x10f00080

[t=0x0000000d:6a86986b] [tid=0x94a41bec] ti.sdo.fc.dman3: [+2] createChannels> Assigning qdmaChannel 1

[t=0x0000000d:6a870ad9] [tid=0x94a41bec] ti.sdo.fc.dman3: [+2] createChannels> Env buffer of size 0x40 requested

[t=0x0000000d:6a878d32] [tid=0x94a41bec] ti.sdo.fc.dman3: [+4] createChannels> Env Allocated memTab[1]: size=0x40, align=0x20, heapId=-1801090328, base=0x10f000c0

[t=0x0000000d:6a883e6e] [tid=0x94a41bec] ti.sdo.fc.dman3: [+2] createChannels> Initializing IDMA3_handle

[t=0x0000000d:6a88b256] [tid=0x94a41bec] ti.sdo.fc.dman3: [+E] initHandle> Enter (handle=0x10f00080, dmaTab=0x94a59b90, qdmaChannel=1, env=0x10f000c0, scratchEnv=0x0, context=0x94a535f4)

[t=0x0000000d:6a897c66] [tid=0x94a41bec] ti.sdo.fc.dman3: [+2] initHandle> Initializing IDMA3 handle with 1 tccs, 1 PaRams, qdmaChannel 1, env 0x10f000c0

[t=0x0000000d:6a8a212d] [tid=0x94a41bec] ti.sdo.fc.dman3: [+2] initHandle> Non-zero env handle

[t=0x0000000d:6a8a8c0b] [tid=0x94a41bec] ti.sdo.fc.dman3: [+2] initHandle> paRam block 0x90049e0, tcc Table 0x94a53519

[t=0x0000000d:6a8b1184] [tid=0x94a41bec] ti.sdo.fc.dman3: [+2] initHandle> Call protocol Init function

[t=0x0000000d:6a8b83c2] [tid=0x94a41bec] ti.sdo.fc.dman3: [+X] initHandle> Exit (status=1)

[t=0x0000000d:6a8beb9e] [tid=0x94a41bec] ti.sdo.fc.dman3: [+2] createChannels> Assigned Qdma Channel(s):1

[t=0x0000000d:6a8c60d8] [tid=0x94a41bec] ti.sdo.fc.dman3: [+2] createChannels> Assigned PaRam(s):

[t=0x0000000d:6a8cce0d] [tid=0x94a41bec] ti.sdo.fc.dman3: [+2] createChannels> dmaTab[1].handle's paRamAddr 0x90049e0

[t=0x0000000d:6a8d506c] [tid=0x94a41bec] ti.sdo.fc.dman3: [+2] createChannels> 79 (Addr 0x90049e0)

[t=0x0000000d:6a8dc1d8] [tid=0x94a41bec] ti.sdo.fc.dman3: [+2] createChannels> Assigned Tcc(s):

[t=0x0000000d:6a8e2d32] [tid=0x94a41bec] ti.sdo.fc.dman3: [+2] createChannels> 33

[t=0x0000000d:6a8e98bb] [tid=0x94a41bec] ti.sdo.fc.dman3: [+X] createChannels> Exit (status=0)

[t=0x0000000d:6a8f05f3] [tid=0x94a41bec] ti.sdo.fc.dman3: [+4] DMAN3_createChannels> Assigned Qdma: 0

[t=0x0000000d:6a8f78e2] [tid=0x94a41bec] ti.sdo.fc.dman3: [+4] DMAN3_createChannels> Assigned PaRam(s):

[t=0x0000000d:6a8fece2] [tid=0x94a41bec] ti.sdo.fc.dman3: [+2] DMAN3_createChannels> dmaTab[0].handle's paRamAddr 0x90049c0

[t=0x0000000d:6a907669] [tid=0x94a41bec] ti.sdo.fc.dman3: [+4] DMAN3_createChannels> 78 (Addr 0x90049c0)

[t=0x0000000d:6a90eed9] [tid=0x94a41bec] ti.sdo.fc.dman3: [+4] DMAN3_createChannels> Assigned Tcc(s):

[t=0x0000000d:6a916134] [tid=0x94a41bec] ti.sdo.fc.dman3: [+4] DMAN3_createChannels> 32

[t=0x0000000d:6a91c715] [tid=0x94a41bec] ti.sdo.fc.dman3: [+4] DMAN3_createChannels> Assigned Qdma: 1

[t=0x0000000d:6a923880] [tid=0x94a41bec] ti.sdo.fc.dman3: [+4] DMAN3_createChannels> Assigned PaRam(s):

[t=0x0000000d:6a92aafc] [tid=0x94a41bec] ti.sdo.fc.dman3: [+2] DMAN3_createChannels> dmaTab[1].handle's paRamAddr 0x90049e0

[t=0x0000000d:6a9332c2] [tid=0x94a41bec] ti.sdo.fc.dman3: [+4] DMAN3_createChannels> 79 (Addr 0x90049e0)

[t=0x0000000d:6a93a99a] [tid=0x94a41bec] ti.sdo.fc.dman3: [+4] DMAN3_createChannels> Assigned Tcc(s):

[t=0x0000000d:6a941a5d] [tid=0x94a41bec] ti.sdo.fc.dman3: [+4] DMAN3_createChannels> 33

[t=0x0000000d:6a9486b3] [tid=0x94a41bec] ti.sdo.fc.dman3: [+X] DMAN3_createChannels> Exit (return=0)

[t=0x0000000d:6b762a63] [tid=0x94a41bec] ti.sdo.fc.dman3: [+E] DMAN3_freeChannels> Enter (channelTab=0x94a59bc0, numChan=2)

[t=0x0000000d:6b76b817] [tid=0x94a41bec] ti.sdo.fc.dman3: [+2] DMAN3_freeChannels> Calling deinit on protocol on Channel 0

[t=0x0000000d:6b774e1d] [tid=0x94a41bec] ti.sdo.fc.dman3: [+2] DMAN3_freeChannels> Calling deinit on protocol on Channel 1

[t=0x0000000d:6b77ddaa] [tid=0x94a41bec] ti.sdo.fc.dman3: [+E] _freeContext> Enter (context=0x94a535f4)

[t=0x0000000d:6b785822] [tid=0x94a41bec] ti.sdo.fc.dman3: [+2] freeContext> Freeing 4 tccs

[t=0x0000000d:6b78ceb5] [tid=0x94a41bec] ti.sdo.fc.dman3: [+2] freeContext> Freeing 4 params

[t=0x0000000d:6b793bda] [tid=0x94a41bec] ti.sdo.fc.dman3: [+2] freeContext> Freeing context memory size 0x30

[t=0x0000000d:6b79b4f4] [tid=0x94a41bec] ti.sdo.fc.dman3: [+X] freeContext> Exit

[t=0x0000000d:6b7a151a] [tid=0x94a41bec] ti.sdo.fc.dman3: [+X] DMAN3_freeChannels> Exit (status=DMAN3_SOK)

The log_prints in the ACPY3 functions are not being displayed, though I know that they are getting called as breakpoints are getting hit.

Update Secundum:

I put a breakpoint at ACPY3_Wait( ), and this is what I see :

Detail of the local variables:

Does this appear reasonable?  Does pending=1 imply that a DMA transfer is actually going on?

Lee Holeva

What runtime code did you add to get the transfer to work ? It is possible, that at runtime, you are enabling trace for only DMAN3. 

Gunjan said:

What runtime code did you add to get the transfer to work ? It is possible, that at runtime, you are enabling trace for only DMAN3. 

This is from the fastcopytest example of Framework 3.21.00.17:

var suffix = Program.build.target.suffix;

/*
 * Set up logging in this cfg file
 */

/*
 * Get a handle to the xdc "Defaults" module that sets default values for
 * the common$ structure. 
 */
var Defaults = xdc.useModule('xdc.runtime.Defaults');

/*
 * Allows names to be displayed in object view tools
 */
Defaults.common$.namedInstance = true;

/*
 * Get a handle to the "Diagnostic mask" that allows enabling/disabling of
 * diagnostics on a permodule basis
 */
var Diags = xdc.useModule('xdc.runtime.Diags');

/*
 * Use one of the loggers provided by osal, this particular one also prints
 * thread ids. In general, it routes events to the system 'printf' function.
 */
var LoggerSys = xdc.useModule('ti.sdo.utils.loggers.LoggerSysTID');
var LoggerSysParams = new LoggerSys.Params();

/*
 * Set the default logger to a created instance of the SYSTID logger
 */
Defaults.common$.logger = LoggerSys.create(LoggerSysParams);

/*
 *  We will use Diags_setMask() in main to enable/disable the trace we want
 *  for various modules, but in order for this to work, we have to set each
 *  of the trace levels to RUNTIME_ON or RUNTIME_OFF. For example, if we
 *  removed the line:
 *      Defaults.common$.diags_ENTRY = Diags.RUNTIME_ON;
 *
 *  below, even if we have the code:
 *
 *      Diags_setMask("ti.sdo.fc.%+E");
 *
 *  in main(), we will not see any of the FC entry level log statements.
 *
 *  Note: We could set the tracing for each module individually, for example,
 *
 *      RMAN.common$.diags_ENTRY = Diags.RUNTIME_ON;
 *
 *  but the Defaults settings apply to all RTSC modules (including Main),
 *  unless specifically overriden on a per-module basis.
 */
Diags.setMaskMeta("xdc.runtime.Defaults", Diags.ALL, Diags.RUNTIME_OFF);

// The following code is to enable logging for metaonly modules ///////////
var Main = xdc.useModule('xdc.runtime.Main');                            //
Diags.setMaskMeta('xdc.runtime.Main', Diags.ALL, Diags.RUNTIME_ON);      //
                                                                         // 
var Registry = xdc.useModule('xdc.runtime.Registry');                    //
                                                                         //
// This line is necessary to prevent Linux apps from seg faulting!       //
Diags.setMaskMeta("xdc.runtime.Registry", Diags.ALL, Diags.RUNTIME_OFF); //
///////////////////////////////////////////////////////////////////////////
/*
 *  @(#) ti.sdo.fc.dman3.examples.fastcopy; 1, 0, 0,3; 3-15-2011 09:54:37; /db/atree/library/trees/fc/fc.git/src/ fc-o17
 */

In my DSP code I have:

  // For logging
  FCSettings_init();
  Diags_setMask(FCSETTINGS_MODNAME"+EX1234567");

  /*
     * Initialize DMA manager and ACPY3 library for XDAIS algorithms
     * and grant DMA resources
  */
  DMAN3_init();
  ACPY3_init();
  //FCPY_init();

The DSP code to do the transfers from external DDR to L1D:

 /* Transfer image rows */
  flip = 0;
  imginPtr = inImg[0];
  imgoutPtr = outImg[0];
  meanVal = 0;

  //Transfer an image row to L1
  TransferRowin(DMAHandle[0], imginPtr, &row_inbuf[flip][0], IMAGEROWSIZE);
  imginPtr+=IMAGEROWSIZE;

  for (k=0;k<IMAGECOLSIZE-1;k++){

    ACPY3_wait(DMAHandle[0]);

    //Transfer an image row to L1
    TransferRowin(DMAHandle[0], imginPtr, &row_inbuf[(flip+1)%2][0], IMAGEROWSIZE);
    imginPtr+=IMAGEROWSIZE;

    // update the mean value
    for (j=0;j<IMAGEROWSIZE;j++){

      pixVal = row_inbuf[flip][j];
      meanVal += (UInt32)pixVal;
    }

    flip = (flip+1)%2;

  }

  //Wait for the last DMA transfer to finish
  ACPY3_wait(DMAHandle[0]);

The TransferRowin function:

/*
Transfer image row in to L1DSRAM
*/
void TransferRowin(IDMA3_Handle h, Int8 *Scr, Int8 *Des, int numBytes)
{
    ACPY3_Params p;
 
    /* Setting up the parameters for the  transfer (data grp 1) */
    p.transferType = ACPY3_1D1D;
    p.dstAddr = (void *)Des;
    p.srcAddr = (void *)Scr;
    p.elementSize = numBytes;
    p.numElements = 1;
    p.numFrames = 1;
    p.waitId = -1;

     /*
     * Configure transfer number 0 on the active DMA handle with the
     * parameters set up above
     */
    ACPY3_configure(h, &p, 0);
   
    /* Submit the transfer configured on the logical channel handle */
    ACPY3_start(h);  
}

Though I'm getting a IDMA_Handle, the DMA transfer is still not working as I am not getting data where I want it.

Lee Holeva

Your logging entries in the .cfg file look fine. Also the runtime code looks right, it should enable trace for all FC components being used, not just DMAN3.  You could try adding the following line, right after calling ACPY3_init():

Diags_setMask(ACPY3_MODNAME"+EX1234567");

This should already be taken care of with the Diags mask you set for FCSETTINGS, but maybe you can give this a quick shot anyway.

I'll try my fastcopy example (from the .17 build) on the 816X evm again here, and try and enable logging to see if that works fine. It may be good to have a reference DMA example working on your board first, before we make the modifications you need.

Gunjan said:

You could try adding the following line, right after calling ACPY3_init():

Diags_setMask(ACPY3_MODNAME"+EX1234567");

This made no difference at all, I still am not getting the ACPY3 log_prints.

Lee Holeva

There is EDMA Linux driver resource conflict with DSP. Please see here: http://e2e.ti.com/support/dsp/integra_dsparm/f/625/t/114858.aspx

Basically it looks like Linux EDMA driver owns all the PaRamSet and TCC resources. None are allocated to the DSP.

Hope this helps.

RV

RV said:

There is EDMA Linux driver resource conflict with DSP. Please see here: http://e2e.ti.com/support/dsp/integra_dsparm/f/625/t/114858.aspx

Basically it looks like Linux EDMA driver owns all the PaRamSet and TCC resources. None are allocated to the DSP.

So this means for now, no DMA for the DSP?  What about programming the EDMA3 LLD for DMA, as this is documented as supporting  the TI816x devices?

Lee Holeva

Lee,

Just to let you know, I  managed to get the dman3/examples/fastcopytest running on the 674 of TI816X EVM running with no issues. I see the memory updated etc. My team is investigating the ACPY3 trace issue, I ran into that as well.

If you want, I can share the contents of my example for you to try out, but looks like you already have some clue ? DMA resources may not be available for use by the DSP ? Questions specifically regarding Integra's Linux driver, might belong on an Integra specific forum, I doubt they'll get much traction here.

Gunjan.

Gunjan said:

Lee,

Just to let you know, I  managed to get the dman3/examples/fastcopytest running on the 674 of TI816X EVM running with no issues. I see the memory updated etc. My team is investigating the ACPY3 trace issue, I ran into that as well.

If you want, I can share the contents of my example for you to try out, but looks like you already have some clue ? DMA resources may not be available for use by the DSP ? Questions specifically regarding Integra's Linux driver, might belong on an Integra specific forum, I doubt they'll get much traction here.

Gunjan.

Yes, I would like to see your code.  Here is my email:

lee.holeva@crown.com

I'm a bit confused though, how could you get ACPY3 to work, when there are no Param Sets or TCCs available to the DSP?  I'm also looking at the EDMA3 LLD.  According to the documentation, the TI816x devices are supported by it.

Lee Holeva

Gunjan,

Did you have Linux running when you had ACPY3 working ? If so which version of PSP drivers are you using ?  The one in currently released EZSDK is linux-2.6.37-psp04.00.00.10. LLD version is edma3lld_02_11_01_02

No, I didn't have Linux running. My test was a standalone test that runs on the DSP only using "configured" channels that it assumes it owns. It is up to the integrator to configure DMAN3 to use only those channels that are available for use by the DSP, so that there is no resource conflict

Per this user guide link http://e2e.ti.com/support/dsp/integra_dsparm/f/625/t/114858.aspx when Linux (Master) is running no TCC or PaRAMSet are available to DSP (Slave). If that is the case, then how can ACPY3 still work?

DSP  will need atleast some of these (TCC,PaRAMSet) be allocated to it from Linux.

So problem is at the EDMA linux driver level. That driver will have to be modified to free up some of these for DSP use.

RV

ACPY3 definitely needs TCCs and PaRAMS along with QDMA channels to do transfers. Per the referenced post, looks like the issue is in the PSP driver, they don't leave any resources available for the DSP.

I couldn't tell from that post, what exactly Sundaram intends to fix.

Maybe there is a way to override the default configuration, so that the LInux driver doesn't use all available TCCs PaRAMs and leaves some for the DSP.