I am currently running compliance testing on some DDR2 memory that we are using. Looking over the JEDEC DDR2 specification (JESD79-2B), there are a few unclear descriptions of the test conditions.
1.) The descriptions for tHZDQ, tLZDQ, tLZDQS are unclear where the endpoint exists that specifies the transition from driving to high-impedance and vice-versa. See pg.98 in the attached (pg. 90 using the page numbering within the document).
2.) The specifications for tHZDQ, tLZDQ, and tLZDQS refers to the "associated clock signal crossing". Can this crossing be a falling edge, or must it be only a rising edge?
Thanks,
Eric