SRIO register setting problem

Travis,

Thank you for your suggestion. We can run write_cmd_test correctly but we have another problem to read data from SRIO switch by maintenance read cmd. We get the time-out error. Does anyone can help for us, please?

/*
 * ============================================================================
 *   @func   test_read_cmd
 *
 *   @desc
 *      The function tests the WRITE command by sending data to the specified
 *      destination ID using Direct IO transfer.
 * ============================================================================
 */
static Int32 test_read_cmd (CSL_SrioHandle hSrio)
{
    volatile Uint32             index;
    volatile Uint8*             dst=DST;
    CSL_SrioDirectIO_ConfigXfr  lsu_conf;
    CSL_SrioPortData            response;
    CSL_SrioLsuCompStat         completionCode;
    Uint32                      intStatus;
    Int32                       counter = 1;

    /* Send out the data */
    while (counter < 11)
    {
        printf ("Debug: Starting Transfer %d on SRIO Port %d\n", counter, SRIO_PORT_NUMBER);

        /* Read the Port Error Status register. */
        response.index = SRIO_PORT_NUMBER;
        CSL_srioGetHwStatus (hSrio, CSL_SRIO_QUERY_SP_ERR_STAT, &response);

        /* Was there an error detected? */
        if ((response.data & ~0x2) != 0)
        {
            /* Error was detected; we need to clear this before we can proceed... */
            printf ("Error: Port %d has Input/Output Error... clearing\n", SRIO_PORT_NUMBER);

            /* Clearing the errors... */
            CSL_srioHwControl (hSrio, CSL_SRIO_CMD_SP_ERR_STAT_CLEAR, &response);
        }
   
        /* Setup the source and destination */
        for(index=0; index<TRANSFER_SIZE; index++)
        {
         src[index] = index;
         dst[index] = 0;
     }

        /* Create an LSU configuration */
        lsu_conf.srcNodeAddr           = (Uint32)&src[0];       /* Source address */
        lsu_conf.dstNodeAddr.addressLo = (Uint32)DST;           /* Destination address          */
     lsu_conf.dstNodeAddr.addressLo = 0;                      /* Destination address          */
        lsu_conf.byteCnt               = TRANSFER_SIZE;         /* Size of data being sent.     */
        lsu_conf.idSize                = 1;                     /* 16 bit device id             */
        lsu_conf.priority              = 2;                     /* PKT priority is 2            */
        lsu_conf.xambs                 = 0;                     /* Not an extended address      */
        lsu_conf.dstId                 = DST_LARGE_DEV_ID;      /* Destination ID               */
        lsu_conf.intrReq               = 1;                     /* Interrupts                   */
        lsu_conf.pktType               = CSL_SRIO_REQ_MAINT_RD;  /* Read with no response       */
        lsu_conf.hopCount              = 0;                     /* Valid for maintainance pkt   */
        lsu_conf.doorbellInfo          = 0;                     /* Not a doorbell pkt           */
        lsu_conf.outPortId             = SRIO_PORT_NUMBER;      /* Tx on the specific SRIO Port.*/

        /* Configure the LSU and start transmission */
        CSL_srioLsuSetup (hSrio, &lsu_conf, 0);

        /* Check if the LSU will generate interrupts or not? */
        if (lsu_conf.intrReq == 0)
        {
            /* No Interrupts: Wait for the completion of transfer */
            response.index = 0;
            while (1)
            {
                /* Poll and check if the LSU has completed */
                CSL_srioGetHwStatus (hSrio, CSL_SRIO_QUERY_LSU_BSY_STAT, &response);

                /* Is the LSU not busy */
                if (response.data == 0)
                    break;
            }
        }
        else
        {
            /* Interrupt: Check for the LSU Interrupt Condition Status Register bits */
            while (1)
            {
                CSL_srioGetLsuIntrStat (hSrio, &intStatus);
                if (intStatus != 0)
                    break;
            }
        }

        /* Get the completion Code for the specific LSU. */
        completionCode.portNum = CSL_SRIO_PORT_0;
        CSL_srioLsuCompCodeStat(hSrio, &completionCode);
        if (completionCode.lsuCompCode == 0x0)
        {
            /* Successfull Transfer. */
            printf ("Debug: SRIO Transfer %d was completed...\n", counter);
        }
        else
        {
            /* Failed Transfer. */
            printf ("Error: SRIO Read Transfer %d has a completion code of %d\n",
                     counter, completionCode.lsuCompCode);
            return -1;
        }

        /* Increment the counter.... */
        counter++;

        /* Delay for some time before we send the next data. */
        delay (1000000);
    }

    /* Test Passed... */
    return 0;
}

Travis,

Thank you for your recommendation. We can get the NWRITE and NREAD packets. There are something that we need to modify.

1. enableSRIO function to clear the SRIO error bit
2. disable port1 and setting SRIO timing for MPY 10x and half rate for our target board.
3. set TRANSFER_SIZE as 4 bytes, DESTID as 0x0 and  HOP_COUNT as 0.

Thank you for your kind and help.

please

i have just began my studies on SRIO on Direct IO and i want just to understand what about the ohter core in the case of NWRITE transaction?

in fact,we setup this program (of NWRITE)in the source and how about target?do you have the program to do this?

thanks

Hi, Travis,

I have a question about SRIO initialization on TCI6488. I'm using the file you attached. After CSL_srioHwSetup(), the ENTX bit in SERDES_CFGTXn_CNTL is always 0, it means that the transmitter is disable, but the ENRX bit in SERDES_CFGRXn_CNTL is 1. I also tried the code slice from appendix A, it is the same result. Would you please give some suggestion about  this problem, thank you very much.

BTW, I can't find csl_srioAux.h in CSL6488 lib, so I comment some functions(CSL_srioLsuCompCodeStat() and CSL_srioGetLsuIntrStat()).

Best Regards,

Bo

Bo,

The reason that you read the ENTX bit as zero is that it is controlled by SRIO low level hardware state machines, as well as the SERDES_CFGTXn_CNTL MMR bit.  Essentially the MMR bit output is ANDed with the HW control function and this signal is fed to the Serdes registers.  So when you read this bit, it is also indicating the ANDed signal.  Hopefully that makes sense, essentially, you enable it in software, then hardware has ulitimate control over the signal because it enables/disables the transmitter as needed for the statemachines.  When the link is up and running, you should read a 1 on this bit.

The csl_srioAux.h file is found in the csl_c6488_src\inc folder.  Here is a copy.

Regards,

Travis

Hello,

    I am working on a DSP EVM TMS320C6474 and want to implement Serial RapidIO Interface on this board. To implement it, I would like to use the DIO_LIB, which is a function library of TEXAS INSTRUMENT.

    My objectif is to connect the DSP EVM to an other : Altera EVM with FPGA, so I have to use the port 0.

    My problem is the following issue : I can't initialized the port 0 on the DSP EVM.

    When I build the testDIO_WriteNread I get no error, but I stay locked on the file RIO_init.c vith RIO_waitForHw.                                                                                                           

    Can someone help me for this problem.

    Thanks everyone

Alexis,

If you are not getting port_ok, and you physically have everything connected correctly, then either the data rates or the port width configurations are not the same between the two link partners.  If you can run the testDIO_WriteNread example from DSP to DSP using port 1, then you should be able to modify the code to use port 0 instead and talk with the FPGA board.  Just make sure you have the SerDes on the FPGA set up to run at the same rate.  How are you connecting to the FPGA board?  Does it have an AMC connector on it, or are you using some sort of AMC-to-SMA adapter approach.  I'm just thinking that if you have a way of looping back via the AMC connector, then you could test DSP-to-DSP on port 0, and get that working first.

Regards,

Travis

Hello,

Thanks for your answer, I'm not able to modifiy the code code to use port 0, I modified some parameters but when I run I stay lock in the RIO_init() function.

Before to connect the FPGA, I would like to test DSP to DSP on port O and I switched resistors and capacitors to connect DSPs by port 0.

After I use an AMC to SMA connection between DSP and FPGA.

I join to you the code to seen all parameters in order to communicate on port 0.

Regards,

ALEXIS

#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <math.h>

#include <csl.h>
#include <csl_srio.h>
#include <cslr_srio.h>

#include "cslUtils.h"
#include "RIO_defs.h"
#include "RIO_init.h"
#include "DIO_packet.h"
#include "DIO_lsuQueue.h"
#include "COM_bench.h"
#include "COM_genBits.h"
#include "COM_callbacks.h"
#include "COM_callbacks_dat.h"
#include "COM_errHandler.h"

/////////////////////////
// Framework control
#define     TEST_NUM            4
#define     TEST_ALL            0
#define     CLKIN1_INPUT_MHZ    50       // C6455 EVM rev. B: CLKIN1 is 40 MHz    - x25 to get 1GHz CPU
                                                                         // C6455 EVM rev. C: CLKIN1 is 50 MHz    - x20 to get 1GHz CPU
                                                                         // C6474 EVM all rev CLKIN1 is 50.00 MHz if SW5-7 (CoreClkSel) is OFF
                                                                         // C6474 EVM all rev CLKIN1 is 61.44 MHz if SW5-7 (CoreClkSel) is ON
#define     PLLC_PREDIV_CLK       1        // PLLC_PREDIV_CLK - 1 set to register                                                   
#ifdef CHIP_C6455
#define     PLLC_PLLM_CLK         20       // PLLC_PLLM_CLK - 1 set to register
#endif
#ifdef CHIP_C6474
#define     PLLC_PLLM_CLK         20       // PLLC_PLLM_CLK - 1 set to register
#endif


volatile unsigned int verbose = 1;
volatile unsigned int NB_ITERATIONS = 10;
volatile unsigned int ntest=0;
volatile unsigned int testIndex;
volatile unsigned int numOfCases = TEST_NUM;
volatile unsigned int numOfArrays = 2;
volatile unsigned int testBench[2*TEST_NUM];
volatile unsigned int CACHE_TEST = 0;
volatile unsigned int validation = 0;
/* Tested on C6474
 * For forwarding test, need to change cslutils.c to use port 0 and
 * port 1 on the EVM.( hSrio->portEn[0] and [1] set to 1)
 */
volatile unsigned int forwarding = 0;
               
volatile unsigned char testEnable[TEST_NUM] =
    { 
        1,     // NwriteR - 1KB - polling   - top        0
        1,     // NwriteR - 4KB - interrupt - raw        1
        1,     // Swrite  - 1KB - polling   - top        2
        1,     // Swrite  - 2KB - interrupt - raw        3
    };         

typedef struct {
        const unsigned char name[16];
        RIO_Ftype fType; Uint8 tType;
        RIO_PacketPrio prioLevel;
        RIO_LsuNum lsuNum; DIO_CompCtrl  compCtrl;
        Uint16 dstId; Uint16 byteCnt;
        Uint32* slaveAddr;
        DIO_NotifyOp opNotifier; Uint16 doorbellInfo;
        /* test buffer pointers */
        Uint32* d_write; Uint32* d_read;
        /* Indicating raw LSU setup (for max speed) */
        Uint32  raw_lsu_setup;
        } TestObj;


//////////////////////
// Global variables
RIO_SrioObj                 srioObj;
RIO_SrioHandle              hSrioDirectIO = &srioObj;
DIO_DataObj                 writeReqObj[TEST_NUM]; // Master write followed by read for validation
DIO_DataObj                 readReqObj[TEST_NUM];
DIO_DoorbellObj             dbellSignal;
#pragma DATA_ALIGN(preConfiglsuRegs, 128);
DIO_LsuRegsToIdma           preConfiglsuRegs;
volatile TestObj                     testObjTab[TEST_NUM] = {
    {//NWRITER - NREAD
      "NWriteR",
      RIO_FTYPE_WRITE,                   (Uint8)RIO_WRITE_TTYPE_NWRITER,
      RIO_PACKET_PRIO_MEDIUM,
      RIO_LSU_0,                           DIO_COMP_CTRL_POLL,
      (Uint16)0xBEEF, /* DestId */         1024, /* NumBytes - max 4Kbytes */
      #ifdef CHIP_C6455  
      (Uint32*)0x900000, /* RapidIO destination addr - Slave DSP (0x900000 and beyond (L2/DDR2))*/
      #endif
      #ifdef CHIP_C6474  
      (Uint32*)0x11800000, /* local L2 of core 1 */
      #endif      
      DIO_NOTIFY_NONE, 0x0000,
      NULL, NULL, 0 /* raw_lsu_setup */
    },
    {//NWRITER - NREAD
      "NWriteR",
      RIO_FTYPE_WRITE,                   (Uint8)RIO_WRITE_TTYPE_NWRITER,
      RIO_PACKET_PRIO_MEDIUM,
      RIO_LSU_2,                           DIO_COMP_CTRL_INTR,
      (Uint16)0xBEEF, /* DestId */         4096, /* NumBytes - max 4Kbytes */  
      #ifdef CHIP_C6455  
      (Uint32*)0x900000, /* RapidIO destination addr - Slave DSP (0x900000 and beyond (L2/DDR2))*/
      #endif
      #ifdef CHIP_C6474  
      (Uint32*)0x11800000, /* local L2 of core 1 */
      #endif
      DIO_NOTIFY_NONE, 0x0000,
      NULL, NULL, 1 /* raw_lsu_setup */
    },
    {//SWRITE - NREAD
      "SWrite",
      RIO_FTYPE_SWRITE,                   (Uint8)RIO_SWRITE_TTYPE_DEFAULT,
      RIO_PACKET_PRIO_MEDIUM,
      RIO_LSU_0,                           DIO_COMP_CTRL_INTR,
      (Uint16)0xBEEF, /* DestId */         256, /* NumBytes - max 4Kbytes */  
      #ifdef CHIP_C6455  
      (Uint32*)0x900000, /* RapidIO destination addr - Slave DSP (0x900000 and beyond (L2/DDR2))*/
      #endif
      #ifdef CHIP_C6474  
      (Uint32*)0x11800000, /* local L2 of core 1 */
      #endif
        DIO_NOTIFY_DOORBELL, 16, // notify doorbell #1 to slave
      NULL, NULL, 0 /* raw_lsu_setup */
    },
    {//SWRITE - NREAD
      "SWrite",
      RIO_FTYPE_SWRITE,                   (Uint8)RIO_SWRITE_TTYPE_DEFAULT,
      RIO_PACKET_PRIO_MEDIUM,
      RIO_LSU_0,                           DIO_COMP_CTRL_INTR,
      (Uint16)0xBEEF, /* DestId */         256, /* NumBytes - max 4Kbytes */  
      #ifdef CHIP_C6455  
      (Uint32*)0x900000, /* RapidIO destination addr - Slave DSP (0x900000 and beyond (L2/DDR2))*/
      #endif
      #ifdef CHIP_C6474  
      (Uint32*)0x11800000, /* local L2 of core 1 */
      #endif 
        DIO_NOTIFY_DOORBELL, 1, // notify doorbell #1 to slave
      NULL, NULL, 1 /* raw_lsu_setup */
    }
};
Uint32 *d_in, *d_out; // For memory allocation


int main(void)
{

volatile Int32 count = NB_ITERATIONS;
volatile Uint32 overhead, k, t1, t2, i, portConfig;
#ifdef CHIP_C6474
    DIO_periphAllon();
    printf("The chip is : C6474!\n");
#endif

    // Initialize PLL controller
    if ( DIO_pllcInit((Uint32)PLLC_PREDIV_CLK, (Uint32)PLLC_PLLM_CLK) != CSL_SOK ) return 1;
    // Initialize error handling
    COM_callbacksInit(
      (COM_FxnPtr)COM_errHandler
    );       
   
    srioObj.devIdSize       = RIO_DEVID_SIZE_16BIT;
    srioObj.isHost           = 1;
    srioObj.smallDevId      = (Uint8)0x54; // master DSP ID for DIO tests
    srioObj.largeDevId      = (Uint16)0x4110; // master DSP ID for DIO tests
    srioObj.sMultiCastDevId0 = (Uint8)0x54;    srioObj.lMultiCastDevId0 = (Uint16)0x4110;
    #if (defined CHIP_C6472) || (defined CHIP_C6474)
    srioObj.sMultiCastDevId1 = (Uint8)0x54;    srioObj.lMultiCastDevId1 = (Uint16)0x4110;
    srioObj.sMultiCastDevId2 = (Uint8)0x54;    srioObj.lMultiCastDevId2 = (Uint16)0x4110;
    #endif
    srioObj.destIdCheckMode  = RIO_DEST_ID_CRTL_MODE_C;

    // Forwarding on test #2
    if (forwarding) testObjTab[2].dstId = 0x4110;

    for(i=0;i<RIO_FORWARD_ENTRY_MAX;i++)
    {
        srioObj.packetFwdConfig[i].largeLowBoundDevId = srioObj.largeDevId;
        srioObj.packetFwdConfig[i].largeUpBoundDevId  = srioObj.largeDevId;
        srioObj.packetFwdConfig[i].smallLowBoundDevId = srioObj.smallDevId;   
        srioObj.packetFwdConfig[i].smallUpBoundDevId  = srioObj.smallDevId;
        srioObj.packetFwdConfig[i].outBoundPort       = (CSL_SrioPortNum)0;
    }
    // Setup SRIO port parameters for DIO tests
    DIO_portSetup(&srioObj,RIO_BOOTMODE_0);         // boot mode for port 0
   
    srioObj.edmaStreamingLsu[0].enStreaming = 0;   
    srioObj.edmaStreamingLsu[0].lsuNum      = RIO_LSU_NONE;

    #ifndef CHIP_C6455
    for (i=1;i<RIO_EDMA_STREAM_MAX;i++) {
        srioObj.edmaStreamingLsu[i].enStreaming = 0;
        srioObj.edmaStreamingLsu[i].lsuNum      = RIO_LSU_NONE;
    }
    #endif
    // setup interrupts and set test default int routing
    DIO_intSetup(&(srioObj.intrCondRouting),&(srioObj.edmaStreamingLsu[0]));
    //delay(5000000);
    //CSL_intcHwControl(hIntcDbell,CSL_INTC_CMD_EVTDISABLE,NULL); // disable doorbells
    srioObj.intrPacing[0]    = (Uint32)0x00051615; // 1ms - doorbells' count down in DMA clock cycles (CPU/3 = 333 MHz)
    srioObj.intrPacing[1]    = (Uint32)0x00000000; // 0ms - lsus' count down in DMA clock cycles (CPU/3 = 333 MHz)
    srioObj.intrPacing[4]    = (Uint32)0x00000000; // 0ms - errors' count down in DMA clock cycles (CPU/3 = 333 MHz)
    #ifdef CHIP_C6474
    srioObj.intrPacing[2]    = (Uint32)0x00051615; // 1ms - doorbells' count down in DMA clock cycles (CPU/3 = 333 MHz)
    srioObj.intrPacing[3]    = (Uint32)0x00000000; // 0ms - lsus' count down in DMA clock cycles (CPU/3 = 333 MHz)
    srioObj.intrPacing[4]    = (Uint32)0x00051615; // 1ms - doorbells' count down in DMA clock cycles (CPU/3 = 333 MHz)
    srioObj.intrPacing[5]    = (Uint32)0x00000000; // 0ms - lsus' count down in DMA clock cycles (CPU/3 = 333 MHz)
    #endif
    srioObj.txPriority0Wm    = CSL_SRIO_TX_PRIORITY_WM_0; // 1 to 8 required buffer count
    srioObj.txPriority1Wm    = CSL_SRIO_TX_PRIORITY_WM_0; // 1 to 8 required buffer count
    srioObj.txPriority2Wm    = CSL_SRIO_TX_PRIORITY_WM_0; // 1 to 8 required buffer count
    srioObj.busTransPriority = CSL_SRIO_BUS_TRANS_PRIORITY_1; // next to lowest
    srioObj.flowCntlIdLen[0] = 0x01; // Select flow control ID length 16-bit
    srioObj.flowCntlId[0]    = 0xBEEF; // Destination ID of flow n, slave DSP in DIO tests ~0x4110
    for (i=0; i<RIO_CONGESTION_NUM_FLOWID_MAX; i++)
    {
       srioObj.flowCntlIdLen[i] = (Uint8)0x01;
       srioObj.flowCntlId[i]    = (Uint16)0x0000;
    }
    // initialization function for the SRIO H/W of the TMS320C6455
    RIO_init(&srioObj,0,NULL);                        I stay lock here
    // enable all directIO interrupt sources
    //delay(5000000);
    DIO_intEnable(1,1,1);
    //delay(5000000);
    // check the port #0 configuration
    if (verbose) {
       portConfig = CSL_FEXT(srioObj.hCslObj->regs->PORT[0].SP_CTL, SRIO_SP_CTL_INITIALIZED_PORT_WIDTH);
       if (portConfig == 0x00000002)
              printf("\n SRIO config: Four-lane port\n");
       else if ((portConfig == 0x00000000) || (portConfig == 0x00000001))
              printf("\n SRIO config: Single-lane port\n");
       else {
              printf("\n SRIO config is invalid\n");
              return(1);
       }
    }

    ///////////////
    // Handles init
    for(k=0; k<TEST_NUM; k++) {

#if (TEST_ALL == 0)
      if (testEnable[k])
#endif   
      {
        // Configure this write requests (operation object)
        DIO_setOpFType(&writeReqObj[k],testObjTab[k].fType);
        DIO_setOpTType(&writeReqObj[k],testObjTab[k].tType);
        DIO_setOpPrioLevel(&writeReqObj[k],testObjTab[k].prioLevel);
        DIO_setOpDstId(&writeReqObj[k],testObjTab[k].dstId);
        if (srioObj.portConfig == RIO_PORT_CONFIG_1X_4X_MODE)
            DIO_setOpOutPortId(&writeReqObj[k],0);
        else
#ifdef CHIP_C6455
            DIO_setOpOutPortId(&writeReqObj[k],testObjTab[k].lsuNum); // Link LSU number to outport ID
#endif
#ifdef CHIP_C6474
            if (!forwarding)
              DIO_setOpOutPortId(&writeReqObj[k],1); // On C6474 EVM, only port 1 connects both DSPs
            else
              DIO_setOpOutPortId(&writeReqObj[k],0); // On C6474 EVM, change to connect both ports
#endif
        DIO_setOpCompCtrl(&writeReqObj[k],testObjTab[k].compCtrl);
        DIO_setOpLsuNum(&writeReqObj[k],testObjTab[k].lsuNum);
        // Allocate memory for Tx
        if ((testObjTab[k].d_write  = (unsigned int*)calloc((testObjTab[k].byteCnt+3)>>2,sizeof(unsigned int) ) )==NULL)   
             return 1;

        // Configure this read requests for validation purposes
        DIO_setOpFType(&readReqObj[k],RIO_FTYPE_REQUEST);
        DIO_setOpTType(&readReqObj[k],RIO_REQUEST_TTYPE_NREAD);
        DIO_setOpPrioLevel(&readReqObj[k],testObjTab[k].prioLevel);
        DIO_setOpDstId(&readReqObj[k],testObjTab[k].dstId);
        DIO_setOpOutPortId(&readReqObj[k],DIO_getOpOutPortId(&writeReqObj[k])); // Link LSU number to outport ID
        DIO_setOpCompCtrl(&readReqObj[k],DIO_COMP_CTRL_POLL);
        DIO_setOpLsuNum(&readReqObj[k],testObjTab[k].lsuNum);
        // Allocate memory for Rx
        if ((testObjTab[k].d_read  = (unsigned int*)calloc((testObjTab[k].byteCnt+3)>>2,sizeof(unsigned int) ) )==NULL)   
            return 1;

      }
    }
    // Init the doorbell signal for those operations requiring synch between write and read
    DIO_setOpFType(&dbellSignal,RIO_FTYPE_DOORBELL);
    DIO_setOpTType(&dbellSignal,RIO_DOORBELL_TTYPE_DEFAULT);
    DIO_setOpCompCtrl(&dbellSignal,DIO_COMP_CTRL_POLL);

    // compute measurement overhead
    t1 = COM_startChrono();
    t2 = COM_stopChrono();
    overhead = t2 - t1;
   
    // Initialize testBench arrays
    memset((void*)testBench, 0, numOfArrays * TEST_NUM * sizeof(unsigned int));

    // LSU readiness
    DIO_pollLsuReady(RIO_LSU_0 ,&srioObj);
    DIO_pollLsuReady(RIO_LSU_1 ,&srioObj);
    DIO_pollLsuReady(RIO_LSU_2 ,&srioObj);
    DIO_pollLsuReady(RIO_LSU_3 ,&srioObj);

    /////////////////////////////
    // MAIN TEST LOOP
    //delay(5000000);
do
{
    ntest++;
    //clearBuffers();
   

    for(testIndex=0; testIndex<TEST_NUM; testIndex++)
    {
#if (TEST_ALL == 0)
       if (testEnable[testIndex])
#endif      
       {          
            if (verbose) {
              printf("DIO_dataReq test %d \n", testIndex);
            }
           
            d_in  = testObjTab[testIndex].d_write;
            d_out = testObjTab[testIndex].d_read;
            // Generate bits and copy into handle   
            COM_genBits(d_in, 8*(testObjTab[testIndex].byteCnt),0,0);

            // Configure this write request (data request object)           
            writeReqObj[testIndex].dspAddr     = (Uint32*)d_in;
            #ifdef CHIP_C6474
            writeReqObj[testIndex].dspAddr     = DIO_local2GlobalAddr(d_in);
            #endif
            writeReqObj[testIndex].rapidIOAddr = (Uint64*)testObjTab[testIndex].slaveAddr;
            writeReqObj[testIndex].byteCnt     = (Uint16)testObjTab[testIndex].byteCnt;
            DIO_storeCurLsuCmd(&writeReqObj[testIndex]);

            /* This mode assumes IDMA LSU reg structure pre-configured at app initialization */
            if (testObjTab[testIndex].raw_lsu_setup){
                DIO_setOpCompCtrl(&writeReqObj[testIndex],DIO_COMP_CTRL_INTR);
                DIO_dataReqGetLsuConfig(&writeReqObj[testIndex],&srioObj,&preConfiglsuRegs.lsuSet[DIO_getOpLsuNum(&writeReqObj[testIndex])]);
                preConfiglsuRegs.lsuNum = DIO_getOpLsuNum(&writeReqObj[testIndex]);
            }
            //delay(5000000);
            t1 = COM_startChrono();
            // API under test - Perform DIO write
            if (testObjTab[testIndex].raw_lsu_setup)
                DIO_rawIdmaLsuSetup(&preConfiglsuRegs,srioObj.hCslObj);
            else
                DIO_dataReq(&writeReqObj[testIndex],&srioObj);
            // Interrupt completion mechanism - wait for interruption
            if (DIO_getOpCompCtrl(&writeReqObj[testIndex]) == DIO_COMP_CTRL_INTR) {
                 asm("        IDLE");
            }
            t2 = COM_stopChrono();

            // Check completion code
            if (DIO_getOpCompCode(&writeReqObj[testIndex]) != CSL_SRIO_TRANS_NO_ERR) {
               printf("\t Transaction failed \n");
               return(1);
            }
            DIO_resetCurLsuCmd(&writeReqObj[testIndex]);                   
            testBench[testIndex * numOfArrays] = 6*(t2-t1-overhead);
            if (verbose) {
              printf("  %s of %6d bytes took %6d cycles \n", testObjTab[testIndex].name, \
                                                            testObjTab[testIndex].byteCnt, \
                                                            6*(t2 - t1));
            }

            // if doorbell notification required
            if (testObjTab[testIndex].opNotifier == DIO_NOTIFY_DOORBELL) {
                DIO_setOpPrioLevel(&dbellSignal,DIO_getOpPrioLevel(&writeReqObj[testIndex]));
                DIO_setOpDstId(&dbellSignal,DIO_getOpDstId(&writeReqObj[testIndex]));
                DIO_setOpOutPortId(&dbellSignal,DIO_getOpOutPortId(&writeReqObj[testIndex]));
                DIO_setOpLsuNum(&dbellSignal,DIO_getOpLsuNum(&writeReqObj[testIndex]));
                dbellSignal.info = DIO_dbellInfoFormat(testObjTab[testIndex].doorbellInfo);               
                do { // REQUIRES SLAVE SW TO CLEAR THE DOORBELL STATUS REGISTER
                  DIO_dbellSignal(&dbellSignal,&srioObj);
                } while (DIO_getOpCompCode(&dbellSignal) == CSL_SRIO_RETRY_DRBL_RESP_RCVD);
                if (DIO_getOpCompCode(&dbellSignal) != CSL_SRIO_TRANS_NO_ERR) {
                  printf("\t Transaction failed \n");
                  return(1);
                }
            }

            // Configure this write request (data request object)           
            readReqObj[testIndex].dspAddr     = (Uint32*)d_out;
            #ifdef CHIP_C6474
            readReqObj[testIndex].dspAddr     = DIO_local2GlobalAddr(d_out);
            #endif
            readReqObj[testIndex].rapidIOAddr = (Uint64*)writeReqObj[testIndex].rapidIOAddr;
            readReqObj[testIndex].byteCnt     = (Uint16)writeReqObj[testIndex].byteCnt;

            t1 = COM_startChrono();
            // Read and validate the Tx data
            DIO_dataReq(&readReqObj[testIndex],&srioObj);
            t2 = COM_stopChrono();
            if (DIO_getOpCompCode(&readReqObj[testIndex]) != CSL_SRIO_TRANS_NO_ERR) {
                  printf("\t Transaction failed \n");
               return(1);
            }          
            testBench[testIndex * numOfArrays + 1] = 6*(t2-t1-overhead);
            if (verbose) {
              printf("  NRead of %6d bytes took %6d cycles \n", testObjTab[testIndex].byteCnt, \
                                                            6*(t2 - t1));
            }
           
               /* Check that the copy read back from the slave matches the original pattern */
            if (!(memcmp((void *)d_in, (void *)d_out, testObjTab[testIndex].byteCnt) == 0)) {
               printf("\t Corrupted data during transaction \n");
               return(1);
            }                      

        } //if (testEnable[testIndex])

    } // end for each test index

} while (--count); // end do while loop

    // Free memory
    for(k=0; k<TEST_NUM; k++) {
#if (TEST_ALL == 0)
      if (testEnable[k])
#endif   
      {
        free(testObjTab[k].d_write); testObjTab[k].d_write=NULL;
        free(testObjTab[k].d_read); testObjTab[k].d_read=NULL;
      }
    }
    DIO_intRelease();

    return 0;
}

The BOOTMODE is not for port selection, the port selection is in the DIO_portSetup() function in cslUtils.c in test/tools/ directory. You will be able to see it when you look inside the function (find portEn). BOOTMODE is for booting configuration, if you are not booting through SRIO (i.e just using CCS to load and execute), leave that setting to BOOTMODE_NONE as it was before.

Hello,

I found the problem, one resistor and one capacitor were not at the good configuration and the receiving link was over.

Thanks everyone for you help.

Alexis

hello,

    I try to use SRIO to comunicate between FPGA and DSP.

    When I connect evaluation cards by SMA connectors I have one problem with the register PORT[0].SP_ERR_STAT.

    This register is set to 1 but I wait the following value : 2.

    I don't know where I could find the solution and if it's a soft probem or hard problem.

    Thanks everyone for your help.

Alexis

Alexis,

Refer back to my earlier post, if you don't get Port_ok, then something is not configured correctly between the two ends of the link.  The first thing to do is make sure that you can run your SRIO setup in loopback mode.  Can you connect the SRIO TX to RX via the SMA cables?  If you can get this to work, and are still having trouble with the FPGA to DSP, then you know that the DSP and FPGA configuration (most likely the datarate) is not set up the same.

Travis

hello Tscheck,

    I have an other question to you : As you know I want to connect FPGA and DSP by SMA.

    I use an IP RapidIO Altera and I would like to know if this IP need absolutly a NIOS to operate and to initialize the RapidIO, for me the nios is just here to the ease of using.

    Thanks.

Alexis,

Sorry, I'm not sure what NIOS is??

Travis

Hello travis,

    A nios is an embedded processor for Altera FPGA and has an Avanlon bus. I use a design for the FPGA Stratix IV (Altera) and in my design I have a nios.

Thanks

Alexis,

I am not familiar with the FPGA side of things, though I'd be surprised if the NOIS was required.  You will need to contact your Altera support team to verify.

Regards,

Travis

I have verified with a contact at Altera, that the NOIS is not required.

Regards,

Travis

hello sungyi:

I'm now studying the SRIO of DSP. I meet the similar question with you. My DSP wants to send Maintenance Read opration to the SWITCH for the value of CAR registers, Howvere the opertation is filed, the LSU6 = 0x06. So I want to know if you have done your question. I hope to get your help.

Thanks lot

Barnett

Barnett,

It was my project in 2009 to use C6474 and I did not have board now. I hope the following information can help you to solve it.

1. TI TCI6487 EVM board is connected by Port 1 only but example code is using Port 0. You might check you hardware SRIO connecting pin.
2. Use enableSRIO function to clear the SRIO error bit.
3. set SRIO timing for MPY 10x and half rate for our target board. It depends on your target board for SRIO rate.
4. set TRANSFER_SIZE as 4 bytes, DESTID as 0x0 and  HOP_COUNT as 0. It depends on your hardware and check the parameters to meet your hardware environment.