Hi, I have a problem setting clock on a new board using AM3715 CPU for x-loader. The evaluation board (Mistral OMAP EVM MAIN BOARD REV G) works fine. It uses a 26 MHz crystal . My new board uses 13 MHz crystal. I found that the clock initialization starts with the crystal clock measurement and setting appropriate index to PRM_CLKSEL 0x48306d40. The PLL3 and PLL4 setting values are exactly the same for either 26 MHz or 13 MHz. The platform.S file contains different values for different crystal clocks, but all clocks use the same values. I measured different clocks connecting them internally sys_clkout2. Following my measurements:
Mistral board:
CORE_CLOCK 400 MHz
SYS_CLOCK (Crystal) 26 MHz
96M 96 MHz
56M 56 MHz
New Board
CORE_CLOCK 200 MHz
SYS_CLOCK (Crystal) 13 MHz
96M 2 MHz
56M none
I modified PRM_CLKSRC_CTRL 0x48307270 value writing 0x41 instead of 0x141 on a new board. That stops dividing the input clock by 6.5 I got following results CORE_CLOCK 200 MHz
SYS_CLOCK (Crystal) 13 MHz
96M 48 MHz
56M 28 MHz
I tried to modify values of M and N for PLL4 (before I removed 6.5 times divider) that didn’t provide change I expected. Something is wrong with my understanding.
According to what I see from documents writing 0x181 to PRM_CLKSEL causes 26 MHz divided 13 to yield 2 MHz. For 13 MHz dividing 6.5 provides the same 2 MHz. But by some reason the PLLs are not locked. What happens?
Why providing 13 MHz causes 96M and 56M twice lower then 26/13 = 2MHz?
