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AM3703 Clocking the GPMC Consistently While Varying the OPP

Bernie Thompson TI
Mastermind 41665 points
Other Parts Discussed in Thread: AM3703

From the TRM, the clock that drives the memory interfaces on the AM37xx is tied to the GPMC_FCLK which is tied to the CORE_L3_ICLK clock. The question is, what is the best way to handle the changing of the OPP on the processor (which impacts the L3 clock) without impacting the timing on the GPMC interface?

My impression is that the drivers such as cpufreq handle this already, but is there any documentation or recommendations in this area?

  • 0
    TI__Genius 9190 points

    Bernie,

    Are you asking if it impacts the timing register values?  If that is what you mean then no, it shouldn't impact this because the timing registers are referenced to number of cycles, not time, so it should be good even when the GPMC_FCLK changes. 

    Or are you asking if you can change the MPU clock and leave the GPMC_FCLK the same?  If that is the case then this is possible becuase they are independent.  You can use the clock tree tool for help setting this up:

    http://focus.ti.com/pdfs/wtbu/CTT-OMAP3630ES1.0-v1.6.0.2.zip

  • 0 in reply to Jeff Culverhouse
    TI__Mastermind 41665 points

    Jeff Culverhouse said:
    Or are you asking if you can change the MPU clock and leave the GPMC_FCLK the same? If that is the case then this is possible becuase they are independent.  You can use the clock tree tool for help setting this up:

    This is what I was wondering, on the clock tree tool it also looks like the GPMC is directly driven by L3_ICLK, so it seems that the GPMC_FCLK is dependent on the L3_ICLK, is this correct?

    The concern here comes from the AM3703 datasheet table 4-22, it looks like to go to OPP50 that the L3_ICLK has to drop to 100MHz, while in OPP100 the L3_ICLK will be running upwards of 200MHz. Based on this, it seems like changing from OPP100 to OPP50 would impact the timing of the GPMC directly, possibly by about half, since the L3_ICLK is what the GPMC appears to be basing GPMC_FCLK off of. I understand that the MPU clock and the GPMC_FCLK are independent at a configuration level, but to change between OPPs it looks like they become associated with each other.

    At this point I am guessing that a change to OPP50 from OPP100 just means that your GPMC timings are just going to be slower unless you go into the GPMC timing registers and make adjustments there, is that correct?

  • 0 in reply to Bernie Thompson TI
    TI__Genius 9190 points

    Bernie Thompson said:
    This is what I was wondering, on the clock tree tool it also looks like the GPMC is directly driven by L3_ICLK, so it seems that the GPMC_FCLK is dependent on the L3_ICLK, is this correct?

    That is correct, the GPMC_FCLK is derived from the L3_ICLK.

    Bernie Thompson said:
    The concern here comes from the AM3703 datasheet table 4-22, it looks like to go to OPP50 that the L3_ICLK has to drop to 100MHz, while in OPP100 the L3_ICLK will be running upwards of 200MHz. Based on this, it seems like changing from OPP100 to OPP50 would impact the timing of the GPMC directly, possibly by about half, since the L3_ICLK is what the GPMC appears to be basing GPMC_FCLK off of. I understand that the MPU clock and the GPMC_FCLK are independent at a configuration level, but to change between OPPs it looks like they become associated with each other.

    At this point I am guessing that a change to OPP50 from OPP100 just means that your GPMC timings are just going to be slower unless you go into the GPMC timing registers and make adjustments there, is that correct?

    To do what you want to do you will need to modify the clocks to be different for the OPP settings.  You will have to independently change the clock settings to achieve frequency you want.  The clock tree tool will be the best way to check your values to get what you want.  

  • 0 in reply to Jeff Culverhouse
    Prodigy 30 points

    Hi Jeff,

                 Pls give the clock tree tool download link?