Problem using 512Mb LPDDR with OMAP3530

Daniele Licini

Other Parts Discussed in Thread: SYSCONFIG

I have a problem with my board that mounts an OMAP3530DCUS with a 512Mb LPDDR Micron x32 with this pn. MT46H16M32LFCM-6:B (datasheet link http://www.micron.com//products/ProductDetails.html?product=products/dram/mobile_lpdram/MT46H16M32LFCM-6).

I state that the same board with a mounted LPDDR 1Gb (Micron pn. MT46H32M32LFCM-5:A) works correctly. So the connection I think it is right.

I have modified the register initialization in function sdrc_init in the file board-beagle.c of BAREBOX but after the download of it the board dosn't give me any signal of life or activity (no prompt and no echo with terminal).

I list the init function I'm using...

static void sdrc_init(void)
{
    /* SDRAM software reset */
    /* No idle ack and RESET enable */
    writel(0x12, SDRC_REG(SYSCONFIG));
    sdelay(100);
    /* No idle ack and RESET disable */
    writel(0x10, SDRC_REG(SYSCONFIG));

    /* SDRC Sharing register */
    /* 32-bit SDRAM on data lane [31:0] - CS0 */
    /* pin tri-stated = 1 */
    writel(0x00000100, SDRC_REG(SHARING));

    /* ----- SDRC Registers Configuration --------- */
    /* SDRC_MCFG0 register */
    writel(0x02482099, SDRC_REG(MCFG_0));

    /* SDRC_RFR_CTRL0 register */
    writel(0x4e201, SDRC_REG(RFR_CTRL_0));

    /* SDRC_ACTIM_CTRLA0 register */
    writel(0x8a9dB4C6, SDRC_REG(ACTIM_CTRLA_0));

    /* SDRC_ACTIM_CTRLB0 register */
    writel(0x21114, SDRC_REG(ACTIM_CTRLB_0));

    /* Disble Power Down of CKE due to 1 CKE on combo part */
    writel(0x00000081, SDRC_REG(POWER));

    /* SDRC_MANUAL command register */
    /* NOP command */
    writel(0x00000000, SDRC_REG(MANUAL_0));
    /* Precharge command */
    writel(0x00000001, SDRC_REG(MANUAL_0));
    /* Auto-refresh command */
    writel(0x00000002, SDRC_REG(MANUAL_0));
    /* Auto-refresh command */
    writel(0x00000002, SDRC_REG(MANUAL_0));

    /* SDRC MR0 register Burst length=4 */
    writel(0x00000032, SDRC_REG(MR_0));

    /* SDRC DLLA control register */
    writel(0x0000000A, SDRC_REG(DLLA_CTRL));

    return;
}