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DRA821U: About ECC error information acquisition of SDL.

Part Number: DRA821U

I am using "ti-processor-sdk-rtos-j7200-evm-08_04_00_04/sdl" to test OSPI ECC errors, but fail to get error information.

I use R5_0_0 in the MAIN domain to insert errors into MCU_FSS0_OSPI and retrieve error information.
However, the return value of "SDL_ECC_getErrorInfoAPI" is "SDL_FAIL".

I attached the source code.
Please let me know if there is anything I should check or if there is anything that needs to be fixed.

I refer to the following documents:
  SDL API Guide for J7200
  Software Diagnostics Library (SDL) - J7200 User Guide

ecc_test.c
#include <string.h>
#include <stddef.h>
#include <stdbool.h>
#include <soc.h>
#include <sdl_types.h>
#include <src/sdl/sdl_ecc.h>
#include <src/sdl/sdl_esm.h>
#include <sdl_exception.h>
#include <src/ip/r5/sdl_vim.h>
#include "osal_interface.h"
#include <src/sdl/ecc/soc/j7200/sdl_ecc_soc.h>

/** ------------------------------------------------------------------------------------
 * This structure holds the list of Ram Ids for memory subtypes SDL_MCU_FSS0_1
 * -------------------------------------------------------------------------------------
 */
static SDL_ECC_MemSubType ECC_Test_SDL_MCU_FSS0_1_subMemTypeList[SDL_MCU_FSS0_1_NUM_RAMS] =
{
    SDL_MCU_FSS0_OSPI_OSPI_WRAP_SRAM_RAM_ID,
};

static SDL_ECC_InitConfig_t ECC_Test_SDL_MCU_FSS0_1_initConfig =
{
    .numRams = SDL_MCU_FSS0_1_NUM_RAMS,
    /**< Number of Rams ECC is enabled */
    .pMemSubTypeList = &(ECC_Test_SDL_MCU_FSS0_1_subMemTypeList[0]),
    /**< Sub type list */
};

SDL_ESM_config ECC_Test_esmInitConfig_MCU =
{
     .esmErrorConfig = {0u, 25u}, /* Self test error config */
     .enableBitmap = {0xffffffffu, 0x00180003u, 0xffffffffu,
                 },
      /**< All events enable: except clkstop events for unused clocks */
     .priorityBitmap = {0xffffffffu, 0x00180003u, 0xffffffffu,
                         },
     /**< All events high priority: except clkstop events for unused clocks */
     .errorpinBitmap = {0xffffffffu, 0x00180003u, 0xffffffffu,
                       },
     /**< All events high priority: except clkstop for unused clocks
      *   and selftest error events */
};

void SDL_ECC_applicationCallbackFunction(SDL_ECC_MemType eccMemType,
                                 uint32_t errorSrc,
                                 uint32_t address,
                                 uint32_t ramId,
                                 uint64_t bitErrorOffset,
                                 uint32_t bitErrorGroup)
{
    int32_t retVal = SDL_PASS;

    return retVal;
}

int32_t SDL_ESM_applicationCallbackFunction(SDL_ESM_Inst esmInst,
                                            SDL_ESM_IntType esmIntrType,
                                            uint32_t grpChannel,
                                            uint32_t index,
                                            uint32_t intSrc,
                                            void *arg)
{
    int32_t retVal = SDL_PASS;

    return retVal;
}

int32_t InjectTest(void)
{
    SDL_ErrType_t result;
    int32_t retVal = -1;
    SDL_ECC_ErrorInfo_t pErrorInfo;
    SDL_ECC_MemType eccmemtype;
    SDL_Ecc_AggrIntrSrc eccIntrSrc;
    SDL_ECC_InjectErrorConfig_t injectErrorConfig;

    memset(&injectErrorConfig, 0, sizeof(injectErrorConfig));

    injectErrorConfig.pErrMem = ((uint32_t *)SDL_ECC_aggrTable[SDL_ECC_MCU_FSS0_1_ECC_AGGR].memConfigTable[0].memStartAddr);

    injectErrorConfig.flipBitMask = 0x3;
	injectErrorConfig.chkGrp = 0x0;

    result = SDL_ECC_injectError(SDL_ECC_MCU_FSS0_1_ECC_AGGR,
                                SDL_MCU_FSS0_OSPI_OSPI_WRAP_SRAM_RAM_ID,
                                SDL_INJECT_ECC_ERROR_FORCING_2BIT_ONCE,
                                &injectErrorConfig);
    if (result != SDL_PASS) {
        return retVal;
    }
    
    result = SDL_ECC_getESMErrorInfo(SDL_ESM_INST_MCU_ESM0, SDLR_MCU_ESM0_ESM_LVL_EVENT_MCU_FSS0_OSPI_0_OSPI_ECC_UNCORR_LVL_INTR_0, &eccmemtype, &eccIntrSrc);
    if (result != SDL_PASS) {
        return retVal;
    }
    
    result = SDL_ECC_getErrorInfo(eccmemtype, eccIntrSrc, &pErrorInfo);
    if (result != SDL_PASS) {
        return retVal;
    } 
    return SDL_PASS;
}

int32_t EccTest(void) {
    int32_t result = SDL_PASS;
    int32_t retValue = -1;

    result = SDL_TEST_osalInit();
    if (result != SDL_PASS) {
        return retValue;
    }

    /* Initialize MAIN ESM module - ESM config should be aligned with the desired error events */
    result = SDL_ESM_init(SDL_ESM_INST_MCU_ESM0, &ECC_Test_esmInitConfig_MCU, SDL_ESM_applicationCallbackFunction, 0U);
    if (result != SDL_PASS) {
        return retValue;
    }

    /* Initialize ECC */
    result = SDL_ECC_init(SDL_ECC_MCU_FSS0_1_ECC_AGGR, &ECC_Test_SDL_MCU_FSS0_1_initConfig);
    if (result != SDL_PASS) {
        return retValue;
    }

    result = SDL_ECC_initEsm(SDL_ESM_INST_MCU_ESM0);
    if (result != SDL_PASS) {
        return retValue;
    } 

    result = InjectTest();
    if (result != SDL_PASS) {
        return retValue;
    } 

    return SDL_PASS;
}

  • Hi,

    Is the MCU_FSS0_OSPI0 module enabled and clocked?   If an OSPI boot flow was used prior to the ECC being run, then the answer is likely "yes".  If a different boot mode such as SD boot mode is being used, then it is possible that the module under test is not powered, and could be causing the ECC test to fail.

    Regards,

    kb

  • Hi kb,

    Thank you for your reply.

    I'm using "No boot mode", running "launch.js" in CCS, and I haven't configured MCU_FSS0_OSPI0, so I assume MCU_FSS0_OSPI0 isn't getting power.

    Please tell me how to set MCU_FSS0_OSPI0, which is necessary to perform the ECC test attached last time, and how to check that it is set.

  • We are working to confirm if the SDL has been tested with the no boot mode. 

    Are you able to confirm that you can see the valid operation with OSPI boot mode or SD boot mode?

  • Hi Karthik,

    Currently, I can't confirm the operation with OSPI boot and SD boot in my environment.
    So I am waiting for the results to see if it has been tested in No Boot mode.

    Regards.

  • Hi Karthik,

    Additional Information

    I confirmed the operation of the ECC test attached before with SD boot.
    But the return value of "SDL_ECC_getErrorInfo" API is "SDL_FAIL".

    Regards.

  • Hi,

    I have been able to reproduce the issue and am working on solving it. I will get back to you in a few days.

    Regards,

    Josiitaa

  • Hi,

    I was trying to perform the ECC test using SD Boot Mode and looks like the SDL_ECC_init API fails as the OSPI modules  have not been enabled.

    Additionally, the esmInitConfig parameters that have been set in your source code seem to be different from the ones in the SDK example. Could you let me know based on what these parameters have been set?

    Regards,

    Josiitaa

  • Hi Josiitaa.

    Because "SDL API Guide for J7200" did not explain the setting value of esmInitConfig parameters, I am using the setting described in "4.1.2. Example Usage" of "Software Diagnostics Library (SDL) - J7200 User Guide".

    The SDK example you're referring to seems to differ from the User Guide example I'm referring to.
    Please let me know what documentation you are referring to.
    I don't understand what to set in esmInitConfig parameters.
    Does the SDK example you're referring to have an explanation for the setting value?

    Currently, I cannot enable the OSPI module because OSPI boot is not possible in my environment.
    So, could you please check if the problem occurs with the esmInitConfig parameters set to the correct values with the OSPI module enabled?

    Regards.

  • Hi,

    I will look into the documentation you are referring to as well as any other sources available to set the esmInitConfig parameters along with OSPI boot mode.  Due to the holidays, I am not able to work through all my dependencies. I will look into the issue and get back to you by early January.

    Regards,

    Josiitaa

  • TI team, any update on this ticket?

  • Hi Kevin,

    Sorry for the delay, I am still working on the issue. Will try to resolve it in a few days.

    Regards,

    Josiitaa

  • Hi Kevin,

    We are waiting for an update from our hardware experts regarding this issue. Will keep you posted.

    Regards,

    Josiitaa

  • Hi Tomitama,

    Currently, I cannot enable the OSPI module because OSPI boot is not possible in my environment.

    OSPI boot mode might be required to enable the OPSI modules. How are you planning on testing it? Is this for a future release? What is the need for testing ECC with the MCU_FSS0_OSPI module?

    Regards,

    Josiitaa

  • Hi Josiitaa.

    OSPI boot will be possible in my environment in the future.
    My goal is to generate MCU_OSPI0_ECC_FAIL arbitrarily in software.

    Additional Information
    When executing the "SDL_ecc_aggrSetEccRamIntrPending" API after the "SDL_ECC_getESMErrorInfo" API of the ECC test attached the other day, the return value of the "SDL_ECC_getErrorInfo" API was "SDL_PASS".
    However, I don't think this is the correct behavior since I have not enabled the OPSI module (not in OSPI boot mode).

    Regards.

  • Hi Tomitama,

    The only change that was made was the addition of the "SDL_ecc_aggrSetEccRamIntrPending" API? Or were there any other changes made?

    And this causes the whole test to PASS? Could you share your test logs?

    Thanks,

    Josiitaa

  • Hi Josiitaa.

    I've done some experiments with this error, so there may be other changes.
    I am attaching the test code.

    I confirmed with CCS debug, so there is no test log.

    Regards.

  • 3678.ecc_test.c
    #include <string.h>
    #include <stddef.h>
    #include <stdbool.h>
    #include <soc.h>
    #include <sdl_types.h>
    #include <src/sdl/sdl_ecc.h>
    #include <src/sdl/sdl_esm.h>
    //#include <sdl_exception.h>
    #include <src/ip/r5/sdl_vim.h>
    #include "osal_interface.h"
    #include <src/sdl/ecc/soc/j7200/sdl_ecc_soc.h>
    
    /** ------------------------------------------------------------------------------------
     * This structure holds the list of Ram Ids for memory subtypes SDL_MCU_FSS0_1
     * -------------------------------------------------------------------------------------
     */
    static SDL_ECC_MemSubType ECC_Test_SDL_MCU_FSS0_1_subMemTypeList[SDL_MCU_FSS0_1_NUM_RAMS] =
    {
        SDL_MCU_FSS0_OSPI_OSPI_WRAP_SRAM_RAM_ID,
    };
    
    static SDL_ECC_InitConfig_t ECC_Test_SDL_MCU_FSS0_1_initConfig =
    {
        .numRams = SDL_MCU_FSS0_1_NUM_RAMS,
        /**< Number of Rams ECC is enabled */
        .pMemSubTypeList = &(ECC_Test_SDL_MCU_FSS0_1_subMemTypeList[0]),
        /**< Sub type list */
    };
    
    SDL_ESM_config ECC_Test_esmInitConfig_MCU =
    {
         .esmErrorConfig = {0u, 24u}, /* Self test error config */
         .enableBitmap = {0xffffffffu, 0x00180003u, 0xffffffffu,
                     },
          /**< All events enable: except clkstop events for unused clocks */
         .priorityBitmap = {0xffffffffu, 0x00180003u, 0xffffffffu,
                             },
         /**< All events high priority: except clkstop events for unused clocks */
         .errorpinBitmap = {0xffffffffu, 0x00180003u, 0xffffffffu,
                           },
         /**< All events high priority: except clkstop for unused clocks
          *   and selftest error events */
    };
    
    void SDL_ECC_applicationCallbackFunction(SDL_ECC_MemType eccMemType,
                                     uint32_t errorSrc,
                                     uint32_t address,
                                     uint32_t ramId,
                                     uint64_t bitErrorOffset,
                                     uint32_t bitErrorGroup)
    {
        int32_t retVal = SDL_PASS;
    
        return retVal;
    }
    
    int32_t SDL_ESM_applicationCallbackFunction(SDL_ESM_Inst esmInst,
                                                SDL_ESM_IntType esmIntrType,
                                                uint32_t grpChannel,
                                                uint32_t index,
                                                uint32_t intSrc,
                                                void *arg)
    {
        int32_t retVal = SDL_PASS;
    
        return retVal;
    }
    
    #if 0
    void vd_ESM_Isr(void)
    {
        SDL_ECC_ErrorInfo_t pErrorInfo;
        SDL_ECC_MemType eccmemtype;
        SDL_Ecc_AggrIntrSrc eccIntrSrc;
        SDL_ErrType_t result= SDL_PASS;
        
        memset(&pErrorInfo, 0, sizeof(pErrorInfo));
        
        if (result == SDL_PASS) {
            result = SDL_ECC_getESMErrorInfo(SDL_ESM_INST_MCU_ESM0, SDLR_MCU_ESM0_ESM_LVL_EVENT_MCU_FSS0_OSPI_0_OSPI_ECC_CORR_LVL_INTR_0, &eccmemtype, &eccIntrSrc);
        }
        
        if (result == SDL_PASS) {
            result = SDL_ECC_getErrorInfo(eccmemtype, eccIntrSrc, &pErrorInfo);
        }
    
        /* If the error was due to injecting an error and is from an EDC type, then use SDL_ECC_AGGR_ERROR_SUBTYPE_INJECT */
        if (pErrorInfo.injectBitErrCnt != 0)
        {
            SDL_ECC_clearNIntrPending(eccmemtype, pErrorInfo.memSubType, eccIntrSrc, SDL_ECC_AGGR_ERROR_SUBTYPE_INJECT, pErrorInfo.injectBitErrCnt);
        }
        else
        {
            SDL_ECC_clearNIntrPending(eccmemtype, pErrorInfo.memSubType, eccIntrSrc, SDL_ECC_AGGR_ERROR_SUBTYPE_NORMAL, pErrorInfo.bitErrCnt);
        }
        SDL_ESM_clrNError(SDL_ESM_INST_MCU_ESM0);
    
        /* Ack the interrupt source for the ECC memtype */
        result = SDL_ECC_ackIntr(eccmemtype, eccIntrSrc);
    }
    #endif
    
    int32_t InjectTest(void)
    {
        SDL_ErrType_t result;
        int32_t retVal = -1;
        SDL_ECC_MemType eccmemtype;
        SDL_Ecc_AggrIntrSrc eccIntrSrc;
        SDL_ECC_InjectErrorConfig_t injectErrorConfig;
        SDL_ecc_aggrRegs *pEccAggr;
    
    #if 0
        SDL_ECC_ErrorInfo_t pErrorInfo;
        memset(&pErrorInfo, 0, sizeof(pErrorInfo));
    #endif
    
        memset(&injectErrorConfig, 0, sizeof(injectErrorConfig));
    
        injectErrorConfig.pErrMem = (uint32_t *)(SDL_ECC_aggrTable[SDL_ECC_MCU_FSS0_1_ECC_AGGR].memConfigTable[0].memStartAddr);
    
        injectErrorConfig.flipBitMask = 24;
    	injectErrorConfig.chkGrp = 0x0;
    
        result = SDL_ECC_injectError(SDL_ECC_MCU_FSS0_1_ECC_AGGR,
                                    SDL_MCU_FSS0_OSPI_OSPI_WRAP_SRAM_RAM_ID,
                                    SDL_INJECT_ECC_ERROR_FORCING_1BIT_ONCE,
                                    &injectErrorConfig);
        if (result != SDL_PASS) {
            return retVal;
        }
    
        result = SDL_ECC_getESMErrorInfo(SDL_ESM_INST_MCU_ESM0, SDLR_MCU_ESM0_ESM_LVL_EVENT_MCU_FSS0_OSPI_0_OSPI_ECC_CORR_LVL_INTR_0, &eccmemtype, &eccIntrSrc);
        if (result != SDL_PASS) {
            return retVal;
        }
    
        pEccAggr = SDL_ECC_aggrBaseAddressTable[eccmemtype];
    	(void)SDL_ecc_aggrSetEccRamIntrPending(pEccAggr, SDL_MCU_FSS0_OSPI_OSPI_WRAP_SRAM_RAM_ID, eccIntrSrc);
    
        result = SDL_ECC_getErrorInfo(eccmemtype, eccIntrSrc, &pErrorInfo);
        if (result != SDL_PASS) {
            return retVal;
        }
    
        return SDL_PASS;
    }
    
    int32_t EccTest(void) {
        int32_t result = SDL_PASS;
        int32_t retValue = -1;
    
        result = SDL_TEST_osalInit();
        if (result != SDL_PASS) {
            return retValue;
        }
    
        /* Initialize MCU ESM module - ESM config should be aligned with the desired error events */
        result = SDL_ESM_init(SDL_ESM_INST_MCU_ESM0, &ECC_Test_esmInitConfig_MCU, SDL_ESM_applicationCallbackFunction, 0U);
        if (result != SDL_PASS) {
            return retValue;
        }
    
        /* Initialize ECC */
        result = SDL_ECC_init(SDL_ECC_MCU_FSS0_1_ECC_AGGR, &ECC_Test_SDL_MCU_FSS0_1_initConfig);
        if (result != SDL_PASS) {
            return retValue;
        }
    
        result = SDL_ECC_initEsm(SDL_ESM_INST_MCU_ESM0);
        if (result != SDL_PASS) {
            return retValue;
        } 
    
        result = InjectTest();
        if (result != SDL_PASS) {
            return retValue;
        } 
    
        return SDL_PASS;
    }
    

  • Hi Tomitama,

    We have raised an internal feature requirement to test ECC on the MCU_FSS0_OSPI module. It will come up in the future releases.

    Thanks,

    Josiitaa

  • Hi Tomitama,

    This feature development has been scheduled for the SDK 9.0 release. Closing this thread.

    Thanks,

    Josiitaa