Other Parts Discussed in Thread: TDA4VM, TCAN1043, TCA6424A
I am working on a proof of concept that requires modifying the CAN Profiling demo. The main domain and mcu domain need to be configured to communicate directly using the CAN ports. The first step is to get the demo to work on both mcu1_0 and mcu2_1 in external loopback mode. However, I am working on the J721e EVM with only the Common Processor Board and SOM, no GESI expansion board.
This is okay for running the demo on mcu1_0, since there are only two CAN ports in the mcu domain. Both MCU MCAN0 and MCU MCAN1 are exposed via headers at J31 and J30. However, the demo on mcu2_1 for the main domain is configured to use MCAN4 and MCAN9. These headers are only accessible via the GESI expansion board.
I would like to modify the demo for mcu2_1 to use MCAN0 and MCAN2, since they are exposed to the common processor board at headers J28 and J27. I have made the necessary additions to Can_Cfg, but am running into difficulty in CanApp_Startup. Based on the TRM, the following should be the correct PAD configurations/multiplexing for MCAN0 and MCAN2:
/* MAIN MCAN 0 Tx PAD configuration */ regVal = 0x60000U; CSL_REG32_WR(CSL_CTRL_MMR0_CFG0_BASE + 0x1C20CU, regVal); /* MAIN MCAN 0 Rx PAD configuration */ regVal = 0x60000U; CSL_REG32_WR(CSL_CTRL_MMR0_CFG0_BASE + 0x1C208U, regVal); /* MAIN MCAN 2 Tx PAD configuration */ regVal = 0x60003U; CSL_REG32_WR(CSL_CTRL_MMR0_CFG0_BASE + 0x1C1F4U, regVal); /* MAIN MCAN 2 Rx PAD configuration */ regVal = 0x60003U; CSL_REG32_WR(CSL_CTRL_MMR0_CFG0_BASE + 0x1C1F0U, regVal);
But when I get to enabling these transceivers, I am confused as to what is happening. I understand that the following code is enabling output for certain GPIO pins, but I am having trouble understanding why:
/* Pin mux for CAN STB used in GESI board */
regVal = 0x20007U;
CSL_REG32_WR(CSL_CTRL_MMR0_CFG0_BASE + 0x1C0F4U, regVal);
/* Take MCAN transceiver out of STB mode for MCAN0 */
/* Set Pin direction to output */
regVal = CSL_REG32_RD(CSL_GPIO0_BASE + 0x38U);
regVal &= (~(1U << 0x1BU));
CSL_REG32_WR(CSL_GPIO0_BASE + 0x38U, regVal);
/* Drive Pin to Low */
Dio_WriteChannel(CAN_TRCV_MAIN_DOMAIN_4_9_11, STD_LOW);
/* Read Pin level */
dioPinLevel[0] = Dio_ReadChannel(CAN_TRCV_MAIN_DOMAIN_4_9_11);
/*Read back the pin levels to ensure transceiver is enabled*/
if (STD_LOW != dioPinLevel[0U])
{
AppUtils_Printf(MSG_NORMAL, MSG_APP_NAME
" Error in Enabling CAN Transceiver Main Domain Inst 4,9,11!!!\n");
}
else
{
AppUtils_Printf(MSG_NORMAL, MSG_APP_NAME
" Successfully Enabled CAN Transceiver Main Domain Inst 4,9,11!!!\n");
}
Could someone point me in the right direction to understanding how these GPIO pins interact with the MCAN pins? The rest of the file seems to be geared toward communicating with the GESI board over I2C, is that what these pins are being used for?
