AM623: Implementation with AM62 through-hole vias

Hello Astro, 

Thank you for the query.

Please refer below thread and let me know if this is something that could help.

https://e2e.ti.com/support/processors-group/processors---internal/f/processors---internal-forum/1132110/am623-rtm-of-am62x-amc-package?tisearch=e2e-sitesearch&keymatch=am62x%2525252017x17%25252520package#

Regards,

Sreenivasa

Hello Astro, 

Please refer below additional  thread. 

(+) AM625: AM625 in FCBGA (441-pin) 0.8 mm pitch - Processors forum - Processors - TI E2E support forums

Regards,

Sreenivasa

Hi, Sreenivasa

Thank you for your reply.
The 0.5mm pitch package requires interstitial via holes to be implemented, but the 0.8mm pitch package allows through-hole via hole implementation. And the 0.8mm pitch package will be mass-produced next year. Is the above understanding correct?

Thanks,
Astro

Hello Astro, 

Thank you for the note. 

Your understanding seems correct.

Regards,

Sreenivasa

Hi, Sreenivasa

Is it possible to use an external GPIO as DREQ?
If you can output the timer to an external pin and return that signal to the CPU as DREQ, you can achieve this function.

Alternatively, is it possible to interrupt Cortex-M at a constant cycle, take in data from GPMC in the interrupt handler, and write it to DRAM?

Thanks,
Astro

Sorry, I commented on the wrong thread.