• State TI Thinks Resolved
  • Locked Locked
  • Replies 3 replies
  • Answers 1 answer
  • Subscribers 99 subscribers
  • Views 514 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

66AK2G12: DDR3 initialization sequence

Koichiro Tashiro
Mastermind 22945 points

Part Number: 66AK2G12

Hi,

My customer is referring below documents/file to configure DDR3.
- TRM(SPRUHY8I)
- Keystone II DDR3 Initialization application report (SPRABX7)
- gel file (evmk2g_arm.gel)
evmk2g_arm.txt

Q1: In SPRABX7 Example 4, delay is inserted at DDR PHY reset. 

What is delay value needed here?
In "Example 3. DDR3 PLL Programming", delay is configured as below.
int temp,i, delay = 1000;
Does it work under any conditions (frequency, etc.)?

Q2: In SPRABX7 "Example 7. Leveling Programming", the PHY Initialization register is configured as below;
DDR3A_PIR = 0x0000FF81;

On the other hand, in GEL file (line#2448), the register is configured like this;
DDR3A_PIR =   0x00000F81; //WLADJ - ON
I guess the GEL file is correct, but please confirm.

Q3: According to TRM Table 7-235 "DDR_PHY_PIR Register Field Descriptions", bit#11 WLADJ and bit#9 WL are described as "DDR3 only".

When DDR3L is used, these bits should be left as 0?
DDR3A_PIR = 0x00000581; (or 0x0000F581;)

Thanks and regards,
Koichiro Tashiro

  • 0
    TI__Guru* 93151 points

    Koichiro-san, overall it is best to get examples from the SDKs, which would have the most up to date drivers and sequences for initializing the DDR.  The GELs and or text in the TRM may be more high level and not have the full details

    Q1: The delay after the PHY reset is needed to properly send an active reset to the internal PHY.  I don't see any specific requirement for the length of the assertion.  I would refer to the code in the SDK.  Obviously a for() loop will execute differently at different speeds, so the value is probably very conservative.

    Q2: The 0xF in bits 15:12 enable more training (read/write bit deskew and read/write data eye training).  I would keep these enabled for more optimal training results.  Again, refer to the sequence and configuration in the SDK

    Q3: In this context DDR3 also includes DDR3L devices.  So those bits would apply to both

    Regards,

    James

  • 0 in reply to JJD
    TI__Mastermind 22945 points

    Hi James,

    The customer referred SDK and found below.
    - Delay value is 200usec, so he will use this value.
    - DDR3A_PIR bits 15:12 are zero, so 0x00000F81 will be used.

    Thanks and regards,
    Koichiro Tashiro

  • 0 in reply to Koichiro Tashiro
    TI__Guru* 93151 points

    ok, will close